| /linux/drivers/clk/stm32/ |
| H A D | clk-stm32-core.h | 163 #define STM32_CLOCK_CFG(_binding, _clk, _sec_id, _struct, _register)\ argument
167 .clock_cfg = (_struct) {_clk},\
171 #define STM32_MUX_CFG(_binding, _clk, _sec_id)\ argument
172 STM32_CLOCK_CFG(_binding, &(_clk), _sec_id, struct clk_stm32_mux *,\
175 #define STM32_GATE_CFG(_binding, _clk, _sec_id)\ argument
176 STM32_CLOCK_CFG(_binding, &(_clk), _sec_id, struct clk_stm32_gate *,\
179 #define STM32_DIV_CFG(_binding, _clk, _sec_id)\ argument
180 STM32_CLOCK_CFG(_binding, &(_clk), _sec_id, struct clk_stm32_div *,\
183 #define STM32_COMPOSITE_CFG(_binding, _clk, _sec_id)\ argument
184 STM32_CLOCK_CFG(_binding, &(_clk), _sec_id, struct clk_stm32_composite *,\
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| /linux/include/linux/ |
| H A D | sh_clk.h | 200 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } argument
201 #define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk } argument
202 #define CLKDEV_ICK_ID(_cid, _did, _clk) { .con_id = _cid, .dev_id = _did, .clk = _clk } argument
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| /linux/arch/arm/mach-omap2/ |
| H A D | omap_hwmod.c | 635 } else if (oh->_clk) { in _get_clkdm()
636 if (!omap2_clk_is_hw_omap(__clk_get_hw(oh->_clk))) in _get_clkdm()
638 clk = to_clk_hw_omap(__clk_get_hw(oh->_clk)); in _get_clkdm()
832 oh->_clk = clk; in _init_main_clk()
838 oh->_clk = clk_get(NULL, oh->main_clk); in _init_main_clk()
841 if (IS_ERR(oh->_clk)) { in _init_main_clk()
854 clk_prepare(oh->_clk); in _init_main_clk()
887 os->_clk = c; in _init_interface_clks()
896 clk_prepare(os->_clk); in _init_interface_clks()
924 oc->_clk = c; in _init_opt_clks()
[all …]
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| H A D | omap_hwmod.h | 181 struct clk *_clk; member
244 struct clk *_clk; member
585 struct clk *_clk; member
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| H A D | display.c | 383 clk_prepare_enable(oc->_clk); in omap_dss_reset()
409 clk_disable_unprepare(oc->_clk); in omap_dss_reset()
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| /linux/drivers/cpufreq/ |
| H A D | rcpufreq_dt.rs | 44 _clk: Clk, field
145 _clk: clk, in init()
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| /linux/Documentation/devicetree/bindings/media/ |
| H A D | cdns,csi2tx.txt | 15 * pixel_if[0-3]_clk: pixel stream output clock, one for each stream
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| /linux/drivers/clk/qcom/ |
| H A D | clk-smd-rpm.c | 109 __DEFINE_CLK_SMD_RPM(_name##_clk, _name##_a_clk, \
114 _name##_clk, _name##_a_clk, QCOM_SMD_RPM_BUS_CLK, r_id, \
119 _name##_clk, _name##_a_clk, QCOM_SMD_RPM_BUS_CLK, r_id, \
129 _name##_clk, _name##_a_clk, \
138 __DEFINE_CLK_SMD_RPM(_name##_clk, _name##_a_clk, \
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| /linux/drivers/gpu/drm/mediatek/ |
| H A D | mtk_ddp_comp.c | 631 static void mtk_ddp_comp_clk_put(void *_clk) in mtk_ddp_comp_clk_put() argument
633 struct clk *clk = _clk; in mtk_ddp_comp_clk_put()
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| /linux/drivers/clk/renesas/ |
| H A D | r9a06g032-clocks.c | 165 #define I_GATE(_clk, _rst, _rdy, _midle, _scon, _mirack, _mistat) { \ argument
166 .gate = _clk, \
|