Searched refs:__DML2_WRAPPER_MAX_STREAMS_PLANES__ (Results 1 – 7 of 7) sorted by relevance
17 for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) { in dml21_helper_find_dml_pipe_idx_by_stream_id()28 for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) { in dml21_find_dml_pipe_idx_by_plane_id()64 for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) { in find_valid_pipe_idx_for_stream_index()87 struct pipe_ctx *dc_main_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__], in dml21_find_dc_pipes_for_plane() argument88 struct pipe_ctx *dc_phantom_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__], in dml21_find_dc_pipes_for_plane() argument103 memset(dc_main_pipes, 0, sizeof(struct pipe_ctx *) * __DML2_WRAPPER_MAX_STREAMS_PLANES__); in dml21_find_dc_pipes_for_plane()104 memset(dc_phantom_pipes, 0, sizeof(struct pipe_ctx *) * __DML2_WRAPPER_MAX_STREAMS_PLANES__); in dml21_find_dc_pipes_for_plane()
59 struct pipe_ctx *dc_main_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__]; in dml21_calculate_rq_and_dlg_params()60 struct pipe_ctx *dc_phantom_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__] = {0}; in dml21_calculate_rq_and_dlg_params()277 struct pipe_ctx *dc_main_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__]; in dml21_prepare_mcache_programming()278 struct pipe_ctx *dc_phantom_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__] = {0}; in dml21_prepare_mcache_programming()
691 for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) { in map_stream_to_dml21_display_cfg()713 for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) { in map_plane_to_dml21_display_cfg()778 …T(disp_cfg_stream_location >= 0 && disp_cfg_stream_location < __DML2_WRAPPER_MAX_STREAMS_PLANES__); in dml21_map_dc_state_into_dml_display_cfg()804 …ERT(disp_cfg_plane_location >= 0 && disp_cfg_plane_location < __DML2_WRAPPER_MAX_STREAMS_PLANES__); in dml21_map_dc_state_into_dml_display_cfg()906 for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) { in dml21_map_hw_resources()
86 for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) { in find_disp_cfg_idx_by_plane_id()92 return __DML2_WRAPPER_MAX_STREAMS_PLANES__; in find_disp_cfg_idx_by_plane_id()99 for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) { in find_disp_cfg_idx_by_stream_id()105 return __DML2_WRAPPER_MAX_STREAMS_PLANES__; in find_disp_cfg_idx_by_stream_id()1062 …signed int odm_mode_array[__DML2_WRAPPER_MAX_STREAMS_PLANES__] = {0}, dpp_per_surface_array[__DML2… in dml2_map_dc_pipes()1076 for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) { in dml2_map_dc_pipes()1083 disp_cfg_index_max = __DML2_WRAPPER_MAX_STREAMS_PLANES__; in dml2_map_dc_pipes()
1144 for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) { in map_stream_to_dml_display_cfg()1191 for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) { in map_plane_to_dml_display_cfg()1208 for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) { in dml2_populate_pipe_to_plane_index_mapping()1213 for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) { in dml2_populate_pipe_to_plane_index_mapping()1306 for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) { in map_dc_state_into_dml_display_cfg()1340 …T(disp_cfg_stream_location >= 0 && disp_cfg_stream_location < __DML2_WRAPPER_MAX_STREAMS_PLANES__); in map_dc_state_into_dml_display_cfg()1380 …ERT(disp_cfg_plane_location >= 0 && disp_cfg_plane_location < __DML2_WRAPPER_MAX_STREAMS_PLANES__); in map_dc_state_into_dml_display_cfg()
83 if (i >= __DML2_WRAPPER_MAX_STREAMS_PLANES__) { in map_hw_resources()85 __func__, i, __DML2_WRAPPER_MAX_STREAMS_PLANES__); in map_hw_resources()
197 for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) { in dml2_helper_find_dml_pipe_idx_by_stream_id()208 for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) { in find_dml_pipe_idx_by_plane_id()