Searched refs:X86_CONFIG (Results 1 – 3 of 3) sorted by relevance
| /linux/arch/x86/kernel/cpu/resctrl/ |
| H A D | pseudo_lock.c | 441 perf_miss_attr.config = X86_CONFIG(.event = 0xd1, in resctrl_arch_measure_l2_residency()
443 perf_hit_attr.config = X86_CONFIG(.event = 0xd1, in resctrl_arch_measure_l2_residency()
480 perf_hit_attr.config = X86_CONFIG(.event = 0x2e, in resctrl_arch_measure_l3_residency()
482 perf_miss_attr.config = X86_CONFIG(.event = 0x2e, in resctrl_arch_measure_l3_residency()
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| /linux/arch/x86/events/intel/ |
| H A D | core.c | 4370 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16); in intel_pebs_aliases_core2()
4398 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16); in intel_pebs_aliases_snb()
4422 u64 alt_config = X86_CONFIG(.event=0xc0, .umask=0x01, .inv=1, .cmask=16); in intel_pebs_aliases_precdist()
4506 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0xcd, .umask=0x01); in is_mem_loads_event()
4511 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0x03, .umask=0x82); in is_mem_loads_aux_event()
5442 X86_CONFIG(.event=0xc0, .umask=0x01); in erratum_hsw11()
7477 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04); in intel_pmu_init_glc()
7714 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); in intel_pmu_init()
7717 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); in intel_pmu_init()
7911 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); in intel_pmu_init()
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| /linux/arch/x86/events/ |
| H A D | perf_event.h | 705 #define X86_CONFIG(args...) ((union x86_pmu_config){.bits = {args}}).value macro
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