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Searched refs:WREG32_SOC15_NO_KIQ (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dhdp_v4_0.c60 WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1); in hdp_v4_0_invalidate_hdp()
H A Dhdp_v5_0.c46 WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1); in hdp_v5_0_invalidate_hdp()
H A Dsoc15_common.h92 #define WREG32_SOC15_NO_KIQ(ip, inst, reg, value) \ macro
H A Dgfx_v9_4_3.c1675 WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data); in gfx_v9_4_3_update_spm_vmid()
H A Dgfx_v12_0.c3850 WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data); in gfx_v12_0_update_spm_vmid()
H A Dgfx_v11_0.c5403 WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data); in gfx_v11_0_update_spm_vmid()
H A Dgfx_v9_0.c5174 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data); in gfx_v9_0_update_spm_vmid_internal()
H A Dgfx_v10_0.c8251 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data); in gfx_v10_0_update_spm_vmid_internal()