Home
last modified time | relevance | path

Searched refs:WREG32_PCIE (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dumc_v8_7.c197 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, in umc_v8_7_clear_error_count_per_channel()
201 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, in umc_v8_7_clear_error_count_per_channel()
210 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, in umc_v8_7_clear_error_count_per_channel()
214 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, in umc_v8_7_clear_error_count_per_channel()
255 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v8_7_query_correctable_error_count()
265 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v8_7_query_correctable_error_count()
408 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v8_7_err_cnt_init_per_channel()
410 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, UMC_V8_7_CE_CNT_INIT); in umc_v8_7_err_cnt_init_per_channel()
415 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v8_7_err_cnt_init_per_channel()
416 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, UMC_V8_7_CE_CNT_INIT); in umc_v8_7_err_cnt_init_per_channel()
H A Dumc_v8_14.c49 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, in umc_v8_14_clear_error_count_per_channel()
138 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v8_14_err_cnt_init_per_channel()
140 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, UMC_V8_14_CE_CNT_INIT); in umc_v8_14_err_cnt_init_per_channel()
H A Dumc_v6_7.c284 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v6_7_query_correctable_error_count()
294 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v6_7_query_correctable_error_count()
383 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, in umc_v6_7_reset_error_count_per_channel()
387 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, in umc_v6_7_reset_error_count_per_channel()
396 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, in umc_v6_7_reset_error_count_per_channel()
400 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, in umc_v6_7_reset_error_count_per_channel()
H A Dumc_v8_10.c91 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, in umc_v8_10_clear_error_count_per_channel()
313 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v8_10_err_cnt_init_per_channel()
315 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, UMC_V8_10_CE_CNT_INIT); in umc_v8_10_err_cnt_init_per_channel()
H A Damdgpu_xgmi.c1128 WREG32_PCIE(pcs_status_reg, 0xFFFFFFFF); in pcs_clear_status()
1129 WREG32_PCIE(pcs_status_reg, 0); in pcs_clear_status()
H A Damdgpu.h1059 #define WREG32_PCIE(reg, v) amdgpu_reg_pcie_wr32(adev, (reg), (v)) macro
/linux/drivers/gpu/drm/radeon/
H A Dr300.c95 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB); in rv370_pcie_gart_tlb_flush()
97 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); in rv370_pcie_gart_tlb_flush()
166 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); in rv370_pcie_gart_enable()
167 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_start); in rv370_pcie_gart_enable()
169 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp); in rv370_pcie_gart_enable()
170 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0); in rv370_pcie_gart_enable()
171 WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0); in rv370_pcie_gart_enable()
173 WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr); in rv370_pcie_gart_enable()
175 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start); in rv370_pcie_gart_enable()
176 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0); in rv370_pcie_gart_enable()
[all …]
H A Drv6xx_dpm.c135 WREG32_PCIE(PCIE_P_CNTL, tmp); in rv6xx_enable_pll_sleep_in_l1()
H A Drv770_dpm.c128 WREG32_PCIE(PCIE_P_CNTL, tmp); in rv770_enable_pll_sleep_in_l1()