Searched refs:WM_DCFCLK (Results 1 – 13 of 13) sorted by relevance
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/ |
| H A D | dcn42_clk_mgr.c | 646 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; in dcn42_build_watermark_ranges()
647 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; in dcn42_build_watermark_ranges()
649 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn42_build_watermark_ranges()
650 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in dcn42_build_watermark_ranges()
652 if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) { in dcn42_build_watermark_ranges()
654 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0; in dcn42_build_watermark_ranges()
657 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = in dcn42_build_watermark_ranges()
660 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk = in dcn42_build_watermark_ranges()
665 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn42_build_watermark_ranges()
666 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in dcn42_build_watermark_ranges()
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| /linux/drivers/gpu/drm/amd/pm/powerplay/inc/ |
| H A D | smu10_driver_if.h | 65 WM_DCFCLK, enumerator
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| /linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/ |
| H A D | smu13_driver_if_v13_0_5.h | 67 WM_DCFCLK, enumerator
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| H A D | smu13_driver_if_yellow_carp.h | 66 WM_DCFCLK, enumerator
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| H A D | smu12_driver_if.h | 67 WM_DCFCLK, enumerator
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| H A D | smu13_driver_if_v13_0_4.h | 67 WM_DCFCLK, enumerator
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| H A D | smu11_driver_if_vangogh.h | 66 WM_DCFCLK, enumerator
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/ |
| H A D | dcn315_smu.h | 57 WM_DCFCLK, enumerator
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/ |
| H A D | dcn316_smu.h | 56 WM_DCFCLK, enumerator
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| H A D | dcn301_smu.h | 71 WM_DCFCLK, enumerator
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/ |
| H A D | dcn35_smu.h | 65 WM_DCFCLK, enumerator
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
| H A D | dcn31_smu.h | 68 WM_DCFCLK, enumerator
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| /linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| H A D | smu10_hwmgr.c | 1383 table->WatermarkRow[WM_DCFCLK][i].WmType = (uint8_t)0; in smu10_set_watermarks_for_clocks_ranges()
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