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Searched refs:UVD_VCPU_CNTL__TRCE_MUX__SHIFT (Results 1 – 13 of 13) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_3_1_sh_mask.h548 #define UVD_VCPU_CNTL__TRCE_MUX__SHIFT 0xb macro
H A Duvd_4_2_sh_mask.h552 #define UVD_VCPU_CNTL__TRCE_MUX__SHIFT 0xb macro
H A Duvd_4_0_sh_mask.h789 #define UVD_VCPU_CNTL__TRCE_MUX__SHIFT 0x0000000b macro
H A Duvd_5_0_sh_mask.h584 #define UVD_VCPU_CNTL__TRCE_MUX__SHIFT 0xb macro
H A Duvd_6_0_sh_mask.h586 #define UVD_VCPU_CNTL__TRCE_MUX__SHIFT 0xb macro
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_2_5_sh_mask.h2749 #define UVD_VCPU_CNTL__TRCE_MUX__SHIFT … macro
H A Dvcn_2_0_0_sh_mask.h2745 #define UVD_VCPU_CNTL__TRCE_MUX__SHIFT … macro
H A Dvcn_2_6_0_sh_mask.h102 #define UVD_VCPU_CNTL__TRCE_MUX__SHIFT … macro
H A Dvcn_3_0_0_sh_mask.h3807 #define UVD_VCPU_CNTL__TRCE_MUX__SHIFT … macro
H A Dvcn_5_0_0_sh_mask.h3752 #define UVD_VCPU_CNTL__TRCE_MUX__SHIFT … macro
H A Dvcn_4_0_5_sh_mask.h3920 #define UVD_VCPU_CNTL__TRCE_MUX__SHIFT … macro
H A Dvcn_4_0_0_sh_mask.h4053 #define UVD_VCPU_CNTL__TRCE_MUX__SHIFT … macro
H A Dvcn_4_0_3_sh_mask.h4089 #define UVD_VCPU_CNTL__TRCE_MUX__SHIFT … macro