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Searched refs:UVD_VCPU_CNTL__BLK_RST_MASK (Results 1 – 13 of 13) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v5_0_0.c683 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK | UVD_VCPU_CNTL__BLK_RST_MASK; in vcn_v5_0_0_start_dpg_mode()
824 ~UVD_VCPU_CNTL__BLK_RST_MASK); in vcn_v5_0_0_start()
852 UVD_VCPU_CNTL__BLK_RST_MASK, in vcn_v5_0_0_start()
853 ~UVD_VCPU_CNTL__BLK_RST_MASK); in vcn_v5_0_0_start()
856 ~UVD_VCPU_CNTL__BLK_RST_MASK); in vcn_v5_0_0_start()
991 UVD_VCPU_CNTL__BLK_RST_MASK, in vcn_v5_0_0_stop()
992 ~UVD_VCPU_CNTL__BLK_RST_MASK); in vcn_v5_0_0_stop()
H A Dvcn_v4_0_5.c897 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK | UVD_VCPU_CNTL__BLK_RST_MASK; in vcn_v4_0_5_start_dpg_mode()
1092 ~UVD_VCPU_CNTL__BLK_RST_MASK); in vcn_v4_0_5_start()
1120 UVD_VCPU_CNTL__BLK_RST_MASK, in vcn_v4_0_5_start()
1121 ~UVD_VCPU_CNTL__BLK_RST_MASK); in vcn_v4_0_5_start()
1124 ~UVD_VCPU_CNTL__BLK_RST_MASK); in vcn_v4_0_5_start()
1257 UVD_VCPU_CNTL__BLK_RST_MASK, in vcn_v4_0_5_stop()
1258 ~UVD_VCPU_CNTL__BLK_RST_MASK); in vcn_v4_0_5_stop()
H A Dvcn_v4_0_3.c795 tmp |= UVD_VCPU_CNTL__BLK_RST_MASK; in vcn_v4_0_3_start_dpg_mode()
1180 ~UVD_VCPU_CNTL__BLK_RST_MASK); in vcn_v4_0_3_start()
1200 UVD_VCPU_CNTL__BLK_RST_MASK, in vcn_v4_0_3_start()
1201 ~UVD_VCPU_CNTL__BLK_RST_MASK); in vcn_v4_0_3_start()
1205 0, ~UVD_VCPU_CNTL__BLK_RST_MASK); in vcn_v4_0_3_start()
1347 UVD_VCPU_CNTL__BLK_RST_MASK, in vcn_v4_0_3_stop()
1348 ~UVD_VCPU_CNTL__BLK_RST_MASK); in vcn_v4_0_3_stop()
H A Dvcn_v4_0.c982 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK | UVD_VCPU_CNTL__BLK_RST_MASK; in vcn_v4_0_start_dpg_mode()
1180 ~UVD_VCPU_CNTL__BLK_RST_MASK); in vcn_v4_0_start()
1207 UVD_VCPU_CNTL__BLK_RST_MASK, in vcn_v4_0_start()
1208 ~UVD_VCPU_CNTL__BLK_RST_MASK); in vcn_v4_0_start()
1211 ~UVD_VCPU_CNTL__BLK_RST_MASK); in vcn_v4_0_start()
1594 UVD_VCPU_CNTL__BLK_RST_MASK, in vcn_v4_0_stop()
1595 ~UVD_VCPU_CNTL__BLK_RST_MASK); in vcn_v4_0_stop()
H A Dvcn_v2_5.c891 tmp |= UVD_VCPU_CNTL__BLK_RST_MASK; in vcn_v2_5_start_dpg_mode()
1111 ~UVD_VCPU_CNTL__BLK_RST_MASK); in vcn_v2_5_start()
1131 UVD_VCPU_CNTL__BLK_RST_MASK, in vcn_v2_5_start()
1132 ~UVD_VCPU_CNTL__BLK_RST_MASK); in vcn_v2_5_start()
1135 ~UVD_VCPU_CNTL__BLK_RST_MASK); in vcn_v2_5_start()
1472 UVD_VCPU_CNTL__BLK_RST_MASK, in vcn_v2_5_stop()
1473 ~UVD_VCPU_CNTL__BLK_RST_MASK); in vcn_v2_5_stop()
H A Dvcn_v3_0.c1011 tmp |= UVD_VCPU_CNTL__BLK_RST_MASK; in vcn_v3_0_start_dpg_mode()
1231 ~UVD_VCPU_CNTL__BLK_RST_MASK); in vcn_v3_0_start()
1248 UVD_VCPU_CNTL__BLK_RST_MASK, in vcn_v3_0_start()
1249 ~UVD_VCPU_CNTL__BLK_RST_MASK); in vcn_v3_0_start()
1252 ~UVD_VCPU_CNTL__BLK_RST_MASK); in vcn_v3_0_start()
1612 UVD_VCPU_CNTL__BLK_RST_MASK, in vcn_v3_0_stop()
1613 ~UVD_VCPU_CNTL__BLK_RST_MASK); in vcn_v3_0_stop()
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_2_5_sh_mask.h2765 #define UVD_VCPU_CNTL__BLK_RST_MASK … macro
H A Dvcn_2_6_0_sh_mask.h118 #define UVD_VCPU_CNTL__BLK_RST_MASK … macro
H A Dvcn_3_0_0_sh_mask.h3824 #define UVD_VCPU_CNTL__BLK_RST_MASK … macro
H A Dvcn_5_0_0_sh_mask.h3774 #define UVD_VCPU_CNTL__BLK_RST_MASK … macro
H A Dvcn_4_0_5_sh_mask.h3939 #define UVD_VCPU_CNTL__BLK_RST_MASK … macro
H A Dvcn_4_0_0_sh_mask.h4072 #define UVD_VCPU_CNTL__BLK_RST_MASK … macro
H A Dvcn_4_0_3_sh_mask.h4111 #define UVD_VCPU_CNTL__BLK_RST_MASK … macro