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Searched refs:UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK (Results 1 – 15 of 15) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h647 #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK … macro
H A Duvd_3_1_sh_mask.h519 #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x1ffffff macro
H A Duvd_4_2_sh_mask.h523 #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x1ffffff macro
H A Duvd_4_0_sh_mask.h746 #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x01ffffffL macro
H A Duvd_5_0_sh_mask.h555 #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x1ffffff macro
H A Duvd_6_0_sh_mask.h557 #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x1ffffff macro
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h1167 #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK … macro
H A Dvcn_2_5_sh_mask.h2677 #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK … macro
H A Dvcn_2_0_0_sh_mask.h2673 #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK … macro
H A Dvcn_2_6_0_sh_mask.h30 #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK … macro
H A Dvcn_3_0_0_sh_mask.h3735 #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK … macro
H A Dvcn_5_0_0_sh_mask.h3679 #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK … macro
H A Dvcn_4_0_5_sh_mask.h3847 #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK … macro
H A Dvcn_4_0_0_sh_mask.h3981 #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK … macro
H A Dvcn_4_0_3_sh_mask.h4016 #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK … macro