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Searched refs:UVD_SUVD_CGC_STATUS__SRE_H264_VCLK__SHIFT (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_5_0_sh_mask.h766 #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK__SHIFT 0x6 macro
H A Duvd_6_0_sh_mask.h764 #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK__SHIFT 0x6 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h486 #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK__SHIFT … macro
H A Dvcn_2_5_sh_mask.h2116 #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK__SHIFT … macro
H A Dvcn_2_0_0_sh_mask.h3242 #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK__SHIFT … macro
H A Dvcn_2_6_0_sh_mask.h3787 #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK__SHIFT … macro
H A Dvcn_3_0_0_sh_mask.h2858 #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK__SHIFT … macro
H A Dvcn_5_0_0_sh_mask.h3467 #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK__SHIFT … macro
H A Dvcn_4_0_5_sh_mask.h3777 #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK__SHIFT … macro
H A Dvcn_4_0_0_sh_mask.h3911 #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK__SHIFT … macro
H A Dvcn_4_0_3_sh_mask.h3946 #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK__SHIFT … macro