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Searched refs:UVD_MPC_SET_MUXB0__VARB_3__SHIFT (Results 1 – 21 of 21) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h619 #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT macro
H A Duvd_3_1_sh_mask.h500 #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12 macro
H A Duvd_4_2_sh_mask.h504 #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12 macro
H A Duvd_4_0_sh_mask.h517 #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x00000012 macro
H A Duvd_5_0_sh_mask.h536 #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12 macro
H A Duvd_6_0_sh_mask.h538 #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h1126 #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT macro
H A Dvcn_2_5_sh_mask.h2867 #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT macro
H A Dvcn_2_0_0_sh_mask.h2632 #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT macro
H A Dvcn_2_6_0_sh_mask.h2859 #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT macro
H A Dvcn_3_0_0_sh_mask.h3940 #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT macro
H A Dvcn_4_0_5_sh_mask.h4057 #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT macro
H A Dvcn_4_0_0_sh_mask.h4190 #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT macro
H A Dvcn_4_0_3_sh_mask.h4233 #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v4_0_5.c932 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | in vcn_v4_0_5_start_dpg_mode()
1071 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | in vcn_v4_0_5_start()
H A Dvcn_v4_0_3.c831 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | in vcn_v4_0_3_start_dpg_mode()
1157 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | in vcn_v4_0_3_start()
H A Dvcn_v2_0.c897 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | in vcn_v2_0_start_dpg_mode()
1030 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | in vcn_v2_0_start()
H A Dvcn_v4_0.c1017 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | in vcn_v4_0_start_dpg_mode()
1159 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | in vcn_v4_0_start()
H A Dvcn_v1_0.c880 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | in vcn_v1_0_start_spg_mode()
1063 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | in vcn_v1_0_start_dpg_mode()
H A Dvcn_v2_5.c926 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | in vcn_v2_5_start_dpg_mode()
1080 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | in vcn_v2_5_start()
H A Dvcn_v3_0.c1046 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | in vcn_v3_0_start_dpg_mode()
1210 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | in vcn_v3_0_start()