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Searched refs:UVD_MPC_SET_MUXA0__VARA_4_MASK (Results 1 – 14 of 14) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h607 #define UVD_MPC_SET_MUXA0__VARA_4_MASK … macro
H A Duvd_3_1_sh_mask.h485 #define UVD_MPC_SET_MUXA0__VARA_4_MASK 0x3f000000 macro
H A Duvd_4_2_sh_mask.h489 #define UVD_MPC_SET_MUXA0__VARA_4_MASK 0x3f000000 macro
H A Duvd_4_0_sh_mask.h502 #define UVD_MPC_SET_MUXA0__VARA_4_MASK 0x3f000000L macro
H A Duvd_5_0_sh_mask.h521 #define UVD_MPC_SET_MUXA0__VARA_4_MASK 0x3f000000 macro
H A Duvd_6_0_sh_mask.h523 #define UVD_MPC_SET_MUXA0__VARA_4_MASK 0x3f000000 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h1114 #define UVD_MPC_SET_MUXA0__VARA_4_MASK … macro
H A Dvcn_2_5_sh_mask.h2855 #define UVD_MPC_SET_MUXA0__VARA_4_MASK … macro
H A Dvcn_2_0_0_sh_mask.h2620 #define UVD_MPC_SET_MUXA0__VARA_4_MASK … macro
H A Dvcn_2_6_0_sh_mask.h2847 #define UVD_MPC_SET_MUXA0__VARA_4_MASK … macro
H A Dvcn_3_0_0_sh_mask.h3928 #define UVD_MPC_SET_MUXA0__VARA_4_MASK … macro
H A Dvcn_4_0_5_sh_mask.h4045 #define UVD_MPC_SET_MUXA0__VARA_4_MASK … macro
H A Dvcn_4_0_0_sh_mask.h4178 #define UVD_MPC_SET_MUXA0__VARA_4_MASK … macro
H A Dvcn_4_0_3_sh_mask.h4221 #define UVD_MPC_SET_MUXA0__VARA_4_MASK … macro