Searched refs:Sequencer (Results 1 – 15 of 15) sorted by relevance
98 | | HW Sequencer | |118 HW Sequencer includes THC major logic, it gets instruction from MMIO registers to control121 type. That means THC HW Sequencer understands HIDSPI/HIDI2C transfer protocol, and handle480 - THC Sequencer reads the input report header by transmitting read approval as a signal482 - THC Sequencer executes a Input Report Body Read operation corresponding to the value484 - THC DMA engine begins fetching data from the THC Sequencer and writes to host memory486 THC Sequencer signals all data has been read or the THC DMA Read Engine reaches the488 - The THC Sequencer checks for the “Last Fragment Flag” bit in the Input Report Header.489 If it is clear, the THC Sequencer enters an idle state.490 - If the “Last Fragment Flag” bit is enabled the THC Sequencer enters End-of-Frame Processing.[all …]
130 unsigned char Sequencer[5]; /* Video Sequencer */ member
27 uint8_t Sequencer[5]; member
332 regp->Sequencer[NV_VIO_SR_RESET_INDEX] = 0x00; in nv_crtc_mode_set_vga()335 regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x29; in nv_crtc_mode_set_vga()337 regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x21; in nv_crtc_mode_set_vga()338 regp->Sequencer[NV_VIO_SR_PLANE_MASK_INDEX] = 0x0F; in nv_crtc_mode_set_vga()339 regp->Sequencer[NV_VIO_SR_CHAR_MAP_INDEX] = 0x00; in nv_crtc_mode_set_vga()340 regp->Sequencer[NV_VIO_SR_MEM_MODE_INDEX] = 0x0E; in nv_crtc_mode_set_vga()
560 regp->Sequencer[i] = NVReadVgaSeq(dev, head, i); in nv_save_state_vga()573 NVWriteVgaSeq(dev, head, i, regp->Sequencer[i]); in nv_load_state_vga()
129 * Sequencer Interrupt Code308 * Sequencer Interrupt Status857 * CMC Sequencer Byte Count866 * Overlay Sequencer Byte Count875 * Data Channel Sequencer Byte Count1053 * SG Sequencer Byte Count3383 * Sequencer Program Overlay Address.3394 * Sequencer Control 03413 * Sequencer Control 13426 * Sequencer Flags[all …]
604 * Sequencer Control (p. 3-33)622 * Sequencer RAM Data (p. 3-34)636 * Sequencer Address Registers (p. 3-35)1410 * the BIOS. The Sequencer relies on a per-SCB field to1423 * the BIOS. The Sequencer relies in a per-SCB field to control the
555 Sequencer event register select - 0 to 2562 Sequencer current state - 0 to 3.585 Sequencer reset event
156 unsigned char Sequencer[5]; /* Video Sequencer */ member
30 The UCD90120 Power Supply Sequencer and System Health Monitor monitors and
187 Sequencer DRAM parameters and control registers. Used for Self-Refresh
189 Sequencer Information
59 Sequencer:
2 OSS Sequencer Emulation on ALSA
350 - Device node interface for ALSA Sequencer