| /linux/drivers/phy/qualcomm/ |
| H A D | phy-qcom-qmp.h | 76 #define SW_RESET BIT(0) macro
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| H A D | phy-qcom-qmp-usb-legacy.c | 765 qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET); in qmp_usb_legacy_init_dp_com()
856 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); in qmp_usb_legacy_power_on()
885 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); in qmp_usb_legacy_power_off()
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| H A D | phy-qcom-qmp-usbc.c | 1073 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); in qmp_usbc_usb_power_on()
1102 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); in qmp_usbc_usb_power_off()
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| H A D | phy-qcom-qmp-usb.c | 1970 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); in qmp_usb_power_on()
1999 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); in qmp_usb_power_off()
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| H A D | phy-qcom-qmp-combo.c | 4102 qphy_clrbits(com, QPHY_V3_DP_COM_SW_RESET, SW_RESET); in qmp_combo_com_init()
4253 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); in qmp_combo_usb_power_on()
4280 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); in qmp_combo_usb_power_off()
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| /linux/drivers/clk/qcom/ |
| H A D | gdsc.h | 65 #define SW_RESET BIT(3) macro
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| H A D | gpucc-sdm660.c | 253 .flags = CLAMP_IO | SW_RESET | AON_RESET | NO_RET_PERIPH,
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| H A D | gpucc-msm8998.c | 269 .flags = CLAMP_IO | SW_RESET | AON_RESET | NO_RET_PERIPH,
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| H A D | gpucc-qcm2290.c | 320 .flags = RETAIN_FF_ENABLE | POLL_CFG_GDSCR | CLAMP_IO | AON_RESET | SW_RESET,
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| H A D | gpucc-sm6375.c | 379 .flags = CLAMP_IO | SW_RESET | AON_RESET,
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| H A D | gpucc-sar2130p.c | 416 .flags = CLAMP_IO | AON_RESET | SW_RESET,
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| H A D | gpucc-sm6115.c | 416 .flags = CLAMP_IO | SW_RESET | VOTABLE,
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| H A D | gpucc-x1e80100.c | 556 .flags = CLAMP_IO | AON_RESET | SW_RESET | POLL_CFG_GDSCR,
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| H A D | gpucc-sm8650.c | 564 .flags = CLAMP_IO | AON_RESET | SW_RESET | POLL_CFG_GDSCR,
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| H A D | gpucc-sm4450.c | 693 .flags = CLAMP_IO | AON_RESET | SW_RESET | POLL_CFG_GDSCR,
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| H A D | gpucc-sm8450.c | 691 .flags = CLAMP_IO | AON_RESET | SW_RESET | POLL_CFG_GDSCR,
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| H A D | gdsc.c | 293 if (sc->flags & SW_RESET) { in gdsc_enable()
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| /linux/drivers/watchdog/ |
| H A D | asm9260_wdt.c | 50 SW_RESET, enumerator
277 priv->mode = SW_RESET; in asm9260_wdt_get_dt_mode()
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| /linux/drivers/net/dsa/microchip/ |
| H A D | lan937x_reg.h | 53 #define SW_RESET BIT(1) macro
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| H A D | lan937x_main.c | 369 ret = lan937x_cfg(dev, REG_SW_OPERATION, SW_RESET, true); in lan937x_reset_switch()
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| H A D | ksz9477_reg.h | 149 #define SW_RESET BIT(1) macro
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| H A D | ksz9477.c | 360 ksz_cfg(dev, REG_SW_OPERATION, SW_RESET, true); in ksz9477_reset_switch()
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| /linux/sound/soc/tegra/ |
| H A D | tegra210_admaif.h | 76 #define SW_RESET 1 macro
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| H A D | tegra210_admaif.c | 529 regmap_update_bits(admaif->regmap, reset_reg, SW_RESET_MASK, SW_RESET); in tegra210_admaif_cget_mono_to_stereo()
533 !(val & SW_RESET_MASK & SW_RESET), in tegra210_admaif_cget_mono_to_stereo()
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| /linux/arch/arm/boot/dts/nxp/imx/ |
| H A D | imx6qp-prtwd3.dts | 277 "", "", "", "", "", "SW_RESET", "", "",
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