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Searched refs:SSP0 (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/pinctrl/
H A Dpinctrl-lpc18xx.c242 LPC_P(1,0, GPIO, CTIN, EMC, R, R, SSP0, SGPIO, R, 0, ND);
243 LPC_P(1,1, GPIO, CTOUT, EMC, SGPIO, R, SSP0, R, R, 0, ND);
244 LPC_P(1,2, GPIO, CTOUT, EMC, SGPIO, R, SSP0, R, R, 0, ND);
277 LPC_P(3,0, I2S0_RX_SCK, I2S0_RX_MCLK, I2S0_TX_SCK, I2S0_TX_MCLK,SSP0,R,R,R, 0, ND);
280 LPC_P(3,3, R, SPI, SSP0, SPIFI, CGU_OUT,R, I2S0_TX_MCLK, I2S1, 0, HS);
283 LPC_P(3,6, GPIO, SPI, SSP0, SPIFI, R, SSP0_ALT, R, R, 0, ND);
284 LPC_P(3,7, R, SPI, SSP0, SPIFI, GPIO, SSP0_ALT, R, R, 0, ND);
285 LPC_P(3,8, R, SPI, SSP0, SPIFI, GPIO, SSP0_ALT, R, R, 0, ND);
335 LPC_P(9,0, GPIO, MCTRL, R, R, R, ENET, SGPIO, SSP0, 0, ND);
336 LPC_P(9,1, GPIO, MCTRL, R, R, I2S0_TX_WS,ENET, SGPIO, SSP0, 0, ND);
[all …]
/linux/drivers/clk/mxs/
H A Dclk-imx28.c27 #define SSP0 (CLKCTRL + 0x0090) macro
194 clks[ssp0_div] = mxs_clk_div("ssp0_div", "ssp0_sel", SSP0, 0, 9, 29); in mx28_clocks_init()
213 clks[ssp0] = mxs_clk_gate("ssp0", "ssp0_div", SSP0, 31); in mx28_clocks_init()
/linux/Documentation/devicetree/bindings/reset/
H A Dnxp,lpc1850-rgu.txt50 50 SSP0
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dfsl,mxs-pinctrl.txt34 particular function, like SSP0 functioning as mmc0-8bit. That said, the
117 In this example, group node mmc0-8bit defines a group of pins for mxs SSP0
/linux/Documentation/devicetree/bindings/clock/
H A Dlpc1850-cgu.txt61 14 BASE_SSP0_CLK Base clock for SSP0
/linux/arch/arm/boot/dts/nxp/lpc/
H A Dlpc4357-myd-lpc4357.dts565 /* Pin conflict with SSP0, the latter is routed to J17 pin header */
/linux/drivers/clk/nxp/
H A Dclk-lpc18xx-cgu.c234 LPC1XX_CGU_BASE_CLK(SSP0, base_common_src_ids, 0),
H A Dclk-lpc32xx.c248 LPC32XX_CLK_DEFINE(SSP0, "ssp0", 0x0, LPC32XX_CLK_HCLK),
1264 LPC32XX_DEFINE_GATE(SSP0, SSP_CTRL, 0, 0),