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Searched refs:SQ_WAVE_STATUS__SCC_MASK (Results 1 – 12 of 12) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h9988 #define SQ_WAVE_STATUS__SCC_MASK 0x00000001L macro
H A Dgfx_7_2_sh_mask.h12479 #define SQ_WAVE_STATUS__SCC_MASK 0x1 macro
H A Dgfx_8_1_sh_mask.h14757 #define SQ_WAVE_STATUS__SCC_MASK 0x1 macro
H A Dgfx_8_0_sh_mask.h14359 #define SQ_WAVE_STATUS__SCC_MASK 0x1 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h28437 #define SQ_WAVE_STATUS__SCC_MASK … macro
H A Dgc_9_1_sh_mask.h29649 #define SQ_WAVE_STATUS__SCC_MASK … macro
H A Dgc_9_2_1_sh_mask.h29975 #define SQ_WAVE_STATUS__SCC_MASK … macro
H A Dgc_9_4_2_sh_mask.h32706 #define SQ_WAVE_STATUS__SCC_MASK … macro
H A Dgc_11_5_0_sh_mask.h36384 #define SQ_WAVE_STATUS__SCC_MASK … macro
H A Dgc_11_0_0_sh_mask.h41455 #define SQ_WAVE_STATUS__SCC_MASK … macro
H A Dgc_10_1_0_sh_mask.h42750 #define SQ_WAVE_STATUS__SCC_MASK … macro
H A Dgc_11_0_3_sh_mask.h44492 #define SQ_WAVE_STATUS__SCC_MASK … macro