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Searched refs:SQ_EDC_CNT__VGPR3_SEC_COUNT_MASK (Results 1 – 5 of 5) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_1_sh_mask.h342 #define SQ_EDC_CNT__VGPR3_SEC_COUNT_MASK … macro
H A Dgc_9_0_sh_mask.h3255 #define SQ_EDC_CNT__VGPR3_SEC_COUNT_MASK … macro
H A Dgc_9_1_sh_mask.h3103 #define SQ_EDC_CNT__VGPR3_SEC_COUNT_MASK … macro
H A Dgc_9_4_2_sh_mask.h26768 #define SQ_EDC_CNT__VGPR3_SEC_COUNT_MASK … macro
H A Dgc_10_1_0_sh_mask.h8204 #define SQ_EDC_CNT__VGPR3_SEC_COUNT_MASK … macro