Searched refs:SOFT_RST (Results 1 – 4 of 4) sorted by relevance
3 The DEVCPU_GCB:CHIP_REGS have a SOFT_RST register that can be used to reset the
74 #define SOFT_RST BIT(0) /* Core Reset */197 * SOFT_RST must be clear before we write to it. in i3c_hci_software_reset() 201 !(regval & SOFT_RST), 0, 10 * USEC_PER_MSEC); in i3c_hci_software_reset() 207 reg_write(RESET_CONTROL, SOFT_RST); in i3c_hci_software_reset() 210 !(regval & SOFT_RST), 0, 10 * USEC_PER_MSEC); in i3c_hci_software_reset() 72 #define SOFT_RST global() macro
108 #define SOFT_RST 0x1 macro
474 emac_reg_update32(adpt->base + EMAC_DMA_MAS_CTRL, 0, SOFT_RST); in emac_mac_reset()