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Searched refs:SM (Results 1 – 25 of 46) sorted by relevance

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/linux/drivers/net/wireless/ath/ath9k/
H A Dar9003_rtt.c77 val = SM(data28, AR_PHY_RTT_SW_RTT_TABLE_DATA); in ar9003_hw_rtt_load_hist_entry()
80 val = SM(0, AR_PHY_RTT_SW_RTT_TABLE_ACCESS) | in ar9003_hw_rtt_load_hist_entry()
81 SM(1, AR_PHY_RTT_SW_RTT_TABLE_WRITE) | in ar9003_hw_rtt_load_hist_entry()
82 SM(index, AR_PHY_RTT_SW_RTT_TABLE_ADDR); in ar9003_hw_rtt_load_hist_entry()
86 val |= SM(1, AR_PHY_RTT_SW_RTT_TABLE_ACCESS); in ar9003_hw_rtt_load_hist_entry()
95 val &= ~SM(1, AR_PHY_RTT_SW_RTT_TABLE_WRITE); in ar9003_hw_rtt_load_hist_entry()
146 val = SM(0, AR_PHY_RTT_SW_RTT_TABLE_ACCESS) | in ar9003_hw_rtt_fill_hist_entry()
147 SM(0, AR_PHY_RTT_SW_RTT_TABLE_WRITE) | in ar9003_hw_rtt_fill_hist_entry()
148 SM(index, AR_PHY_RTT_SW_RTT_TABLE_ADDR); in ar9003_hw_rtt_fill_hist_entry()
153 val |= SM(1, AR_PHY_RTT_SW_RTT_TABLE_ACCESS); in ar9003_hw_rtt_fill_hist_entry()
H A Dar9002_phy.c239 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); in ar9002_hw_spur_mitigate()
268 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | in ar9002_hw_spur_mitigate()
269 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); in ar9002_hw_spur_mitigate()
320 pll = SM(ref_div, AR_RTC_9160_PLL_REFDIV); in ar9002_hw_compute_pll_control()
321 pll |= SM(pll_div, AR_RTC_9160_PLL_DIV); in ar9002_hw_compute_pll_control()
324 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL); in ar9002_hw_compute_pll_control()
326 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL); in ar9002_hw_compute_pll_control()
462 regval |= SM(antdiv_ctrl1, AR_PHY_9285_ANT_DIV_CTL); in ar9002_hw_set_bt_ant_diversity()
463 regval |= SM(antdiv_ctrl2, AR_PHY_9285_ANT_DIV_ALT_LNACONF); in ar9002_hw_set_bt_ant_diversity()
464 regval |= SM((antdiv_ctrl2 >> 2), AR_PHY_9285_ANT_DIV_MAIN_LNACONF); in ar9002_hw_set_bt_ant_diversity()
[all …]
H A Deeprom_9287.c443 regval = SM(pdGainOverlap_t2, in ath9k_hw_set_ar9287_power_cal_table()
445 | SM(gainBoundaries[0], in ath9k_hw_set_ar9287_power_cal_table()
447 | SM(gainBoundaries[1], in ath9k_hw_set_ar9287_power_cal_table()
449 | SM(gainBoundaries[2], in ath9k_hw_set_ar9287_power_cal_table()
451 | SM(gainBoundaries[3], in ath9k_hw_set_ar9287_power_cal_table()
872 SM(pModal->iqCalICh[i], in ath9k_hw_ar9287_set_board_values()
874 SM(pModal->iqCalQCh[i], in ath9k_hw_ar9287_set_board_values()
905 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) in ath9k_hw_ar9287_set_board_values()
906 | SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF) in ath9k_hw_ar9287_set_board_values()
907 | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON) in ath9k_hw_ar9287_set_board_values()
[all …]
H A Dmac.c33 SM(ah->txok_interrupt_mask, AR_IMR_S0_QCU_TXOK) in ath9k_hw_set_txq_interrupts()
34 | SM(ah->txdesc_interrupt_mask, AR_IMR_S0_QCU_TXDESC)); in ath9k_hw_set_txq_interrupts()
36 SM(ah->txerr_interrupt_mask, AR_IMR_S1_QCU_TXERR) in ath9k_hw_set_txq_interrupts()
37 | SM(ah->txeol_interrupt_mask, AR_IMR_S1_QCU_TXEOL)); in ath9k_hw_set_txq_interrupts()
124 (txcfg & ~AR_FTRIG) | SM(newLevel, AR_FTRIG)); in ath9k_hw_updatetxtriglevel()
391 SM(cwMin, AR_D_LCL_IFS_CWMIN) | in ath9k_hw_resettxqueue()
392 SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX) | in ath9k_hw_resettxqueue()
393 SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS)); in ath9k_hw_resettxqueue()
396 SM(INIT_SSH_RETRY, AR_D_RETRY_LIMIT_STA_SH) | in ath9k_hw_resettxqueue()
397 SM(INIT_SLG_RETRY, AR_D_RETRY_LIMIT_STA_LG) | in ath9k_hw_resettxqueue()
[all …]
H A Dar9002_mac.c227 ctl6 = SM(i->keytype, AR_EncrType); in ar9002_set_txdesc()
243 | SM(0, AR_BurstDur)); in ar9002_set_txdesc()
261 ctl1 |= (i->keyix != ATH9K_TXKEYIX_INVALID ? SM(i->keyix, AR_DestIdx) : 0) in ar9002_set_txdesc()
262 | SM(i->type, AR_FrameType) in ar9002_set_txdesc()
269 ctl6 |= SM(i->aggr_len, AR_AggrLen); in ar9002_set_txdesc()
273 ctl6 |= SM(i->ndelim, AR_PadDelim); in ar9002_set_txdesc()
284 | SM(i->txpower[0], AR_XmitPower0) in ar9002_set_txdesc()
309 | SM(i->rtscts_rate, AR_RTSCTSRate)); in ar9002_set_txdesc()
311 WRITE_ONCE(ads->ds_ctl9, SM(i->txpower[1], AR_XmitPower1)); in ar9002_set_txdesc()
312 WRITE_ONCE(ads->ds_ctl10, SM(i->txpower[2], AR_XmitPower2)); in ar9002_set_txdesc()
[all …]
H A Dar5008_phy.c474 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); in ar5008_hw_spur_mitigate()
484 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | in ar5008_hw_spur_mitigate()
485 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); in ar5008_hw_spur_mitigate()
918 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV); in ar9160_hw_compute_pll_control()
921 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL); in ar9160_hw_compute_pll_control()
923 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL); in ar9160_hw_compute_pll_control()
926 pll |= SM(0x50, AR_RTC_9160_PLL_DIV); in ar9160_hw_compute_pll_control()
928 pll |= SM(0x58, AR_RTC_9160_PLL_DIV); in ar9160_hw_compute_pll_control()
941 pll |= SM(0x1, AR_RTC_PLL_CLKSEL); in ar5008_hw_compute_pll_control()
943 pll |= SM(0x2, AR_RTC_PLL_CLKSEL); in ar5008_hw_compute_pll_control()
[all …]
H A Deeprom_4k.c347 SM(pdGainOverlap_t2, in ath9k_hw_set_4k_power_cal_table()
349 | SM(gainBoundaries[0], in ath9k_hw_set_4k_power_cal_table()
351 | SM(gainBoundaries[1], in ath9k_hw_set_4k_power_cal_table()
353 | SM(gainBoundaries[2], in ath9k_hw_set_4k_power_cal_table()
355 | SM(gainBoundaries[3], in ath9k_hw_set_4k_power_cal_table()
709 SM(pModal->iqCalICh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) | in ath9k_hw_4k_set_gain()
710 SM(pModal->iqCalQCh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF), in ath9k_hw_4k_set_gain()
785 regVal |= SM(ant_div_control1, in ath9k_hw_4k_set_board_values()
787 regVal |= SM(ant_div_control2, in ath9k_hw_4k_set_board_values()
789 regVal |= SM((ant_div_control2 >> 2), in ath9k_hw_4k_set_board_values()
[all …]
H A Dar9003_mac.c74 | SM(0, AR_BurstDur)); in ar9003_set_txdesc()
90 ctl17 = SM(i->keytype, AR_EncrType); in ar9003_set_txdesc()
104 | SM(i->txpower[0], AR_XmitPower0) in ar9003_set_txdesc()
113 SM(i->keyix, AR_DestIdx) : 0) in ar9003_set_txdesc()
114 | SM(i->type, AR_FrameType) in ar9003_set_txdesc()
122 ctl17 |= SM(i->aggr_len, AR_AggrLen); in ar9003_set_txdesc()
126 ctl17 |= SM(i->ndelim, AR_PadDelim); in ar9003_set_txdesc()
136 ctl12 |= SM(val, AR_PAPRDChainMask); in ar9003_set_txdesc()
152 | SM(i->rtscts_rate, AR_RTSCTSRate)); in ar9003_set_txdesc()
156 WRITE_ONCE(ads->ctl20, SM(i->txpower[1], AR_XmitPower1)); in ar9003_set_txdesc()
[all …]
H A Deeprom_def.c440 SM(pModal-> bswMargin[i], AR_PHY_GAIN_2GHZ_BSW_MARGIN), in ath9k_hw_def_set_gain()
443 SM(pModal->bswAtten[i], AR_PHY_GAIN_2GHZ_BSW_ATTEN), in ath9k_hw_def_set_gain()
457 SM(txRxAttenLocal, AR_PHY_RXGAIN_TXRX_ATTEN), in ath9k_hw_def_set_gain()
460 SM(pModal->rxTxMarginCh[i], AR_PHY_GAIN_2GHZ_RXTX_MARGIN), in ath9k_hw_def_set_gain()
499 SM(pModal->iqCalICh[i], in ath9k_hw_def_set_board_values()
501 SM(pModal->iqCalQCh[i], in ath9k_hw_def_set_board_values()
568 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) in ath9k_hw_def_set_board_values()
569 | SM(pModal->txEndToXpaOff, in ath9k_hw_def_set_board_values()
571 | SM(pModal->txFrameToXpaOn, in ath9k_hw_def_set_board_values()
573 | SM(pModal->txFrameToXpaOn, in ath9k_hw_def_set_board_values()
[all …]
H A Dar9003_phy.c581 pll = SM(0x5, AR_RTC_9300_SOC_PLL_REFDIV); in ar9003_hw_compute_pll_control_soc()
584 pll |= SM(0x1, AR_RTC_9300_SOC_PLL_CLKSEL); in ar9003_hw_compute_pll_control_soc()
586 pll |= SM(0x2, AR_RTC_9300_SOC_PLL_CLKSEL); in ar9003_hw_compute_pll_control_soc()
588 pll |= SM(0x2c, AR_RTC_9300_SOC_PLL_DIV_INT); in ar9003_hw_compute_pll_control_soc()
598 pll = SM(0x5, AR_RTC_9300_PLL_REFDIV); in ar9003_hw_compute_pll_control()
601 pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL); in ar9003_hw_compute_pll_control()
603 pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL); in ar9003_hw_compute_pll_control()
605 pll |= SM(0x2c, AR_RTC_9300_PLL_DIV); in ar9003_hw_compute_pll_control()
1453 radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR); in ar9003_hw_set_radar_params()
1454 radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI); in ar9003_hw_set_radar_params()
[all …]
H A Dhw.c723 SM(2, AR_QOS_NO_ACK_TWO_BIT) | in ath9k_hw_init_qos()
724 SM(5, AR_QOS_NO_ACK_BIT_OFF) | in ath9k_hw_init_qos()
725 SM(0, AR_QOS_NO_ACK_BYTE_OFF)); in ath9k_hw_init_qos()
1151 SM(rx_lat, AR_USEC_RX_LAT) | in ath9k_hw_init_global_settings()
1152 SM(tx_lat, AR_USEC_TX_LAT), in ath9k_hw_init_global_settings()
1157 sifstime | SM(ack_shift, AR_TXSIFS_ACK_SHIFT), in ath9k_hw_init_global_settings()
2356 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT) in ath9k_hw_set_sta_beacon_timers()
2365 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT)); in ath9k_hw_set_sta_beacon_timers()
3186 mask |= SM(AR_GENTMR_BIT(timer->index), in ath9k_hw_gen_timer_start()
3189 mask |= SM(AR_GENTMR_BIT(timer->index), in ath9k_hw_gen_timer_start()
[all …]
/linux/drivers/net/wireless/ath/ath6kl/
H A Dhif.c213 SM(INT_STATUS_ENABLE_MBOX_DATA, 0x01); in ath6kl_hif_rx_control()
216 ~SM(INT_STATUS_ENABLE_MBOX_DATA, 0x01); in ath6kl_hif_rx_control()
577 SM(INT_STATUS_ENABLE_ERROR, 0x01) | in ath6kl_hif_enable_intrs()
578 SM(INT_STATUS_ENABLE_CPU, 0x01) | in ath6kl_hif_enable_intrs()
579 SM(INT_STATUS_ENABLE_COUNTER, 0x01); in ath6kl_hif_enable_intrs()
585 dev->irq_en_reg.int_status_en |= SM(INT_STATUS_ENABLE_MBOX_DATA, 0x01); in ath6kl_hif_enable_intrs()
592 SM(ERROR_STATUS_ENABLE_RX_UNDERFLOW, 0x01) | in ath6kl_hif_enable_intrs()
593 SM(ERROR_STATUS_ENABLE_TX_OVERFLOW, 0x1); in ath6kl_hif_enable_intrs()
599 dev->irq_en_reg.cntr_int_status_en = SM(COUNTER_INT_STATUS_ENABLE_BIT, in ath6kl_hif_enable_intrs()
/linux/drivers/net/wireless/ath/ath10k/
H A Dhw.c677 slottime = SM(slottime, WAVE1_PCU_GBL_IFS_SLOT); in ath10k_hw_qca988x_set_coverage_class()
684 ack_timeout = SM(ack_timeout, WAVE1_PCU_ACK_CTS_TIMEOUT_ACK); in ath10k_hw_qca988x_set_coverage_class()
690 cts_timeout = SM(cts_timeout, WAVE1_PCU_ACK_CTS_TIMEOUT_CTS); in ath10k_hw_qca988x_set_coverage_class()
780 reg_val |= (SM(hw_clk->rnfrac, BB_PLL_CONFIG_FRAC) | in ath10k_hw_qca6174_enable_pll_clock()
781 SM(hw_clk->outdiv, BB_PLL_CONFIG_OUTDIV)); in ath10k_hw_qca6174_enable_pll_clock()
793 reg_val |= SM(hw_clk->settle_time, WLAN_PLL_SETTLE_TIME); in ath10k_hw_qca6174_enable_pll_clock()
805 reg_val |= SM(1, SOC_CORE_CLK_CTRL_DIV); in ath10k_hw_qca6174_enable_pll_clock()
823 reg_val |= (SM(hw_clk->refdiv, WLAN_PLL_CONTROL_REFDIV) | in ath10k_hw_qca6174_enable_pll_clock()
824 SM(hw_clk->div, WLAN_PLL_CONTROL_DIV) | in ath10k_hw_qca6174_enable_pll_clock()
825 SM(1, WLAN_PLL_CONTROL_NOPWD)); in ath10k_hw_qca6174_enable_pll_clock()
[all …]
H A Dhtt_tx.c36 return SM(exp, HTT_TX_Q_STATE_ENTRY_EXP) | in ath10k_htt_tx_txq_calc_size()
37 SM(factor, HTT_TX_Q_STATE_ENTRY_FACTOR); in ath10k_htt_tx_txq_calc_size()
704 info |= SM(htt->tx_q_state.type, in ath10k_htt_send_frag_desc_bank_cfg_32()
766 info |= SM(htt->tx_q_state.type, in ath10k_htt_send_frag_desc_bank_cfg_64()
1305 flags0 |= SM(txmode, HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE); in ath10k_htt_tx_hl()
1308 flags0 |= SM(ATH10K_HW_TXRX_MGMT, in ath10k_htt_tx_hl()
1320 flags1 |= SM((u16)vdev_id, HTT_DATA_TX_DESC_FLAGS1_VDEV_ID); in ath10k_htt_tx_hl()
1321 flags1 |= SM((u16)tid, HTT_DATA_TX_DESC_FLAGS1_EXT_TID); in ath10k_htt_tx_hl()
1478 flags0 |= SM(txmode, HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE); in ath10k_htt_tx_32()
1481 flags0 |= SM(ATH10K_HW_TXRX_MGMT, in ath10k_htt_tx_32()
[all …]
H A Dpci.c2962 SM(QCA9887_1_0_I2C_SDA_PIN_CONFIG, in ath10k_pci_enable_eeprom()
2964 SM(1, GPIO_PIN0_PAD_PULL)); in ath10k_pci_enable_eeprom()
2969 SM(QCA9887_1_0_SI_CLK_PIN_CONFIG, GPIO_PIN0_CONFIG) | in ath10k_pci_enable_eeprom()
2970 SM(1, GPIO_PIN0_PAD_PULL)); in ath10k_pci_enable_eeprom()
2980 SM(1, SI_CONFIG_ERR_INT) | in ath10k_pci_enable_eeprom()
2981 SM(1, SI_CONFIG_BIDIR_OD_DATA) | in ath10k_pci_enable_eeprom()
2982 SM(1, SI_CONFIG_I2C) | in ath10k_pci_enable_eeprom()
2983 SM(1, SI_CONFIG_POS_SAMPLE) | in ath10k_pci_enable_eeprom()
2984 SM(1, SI_CONFIG_INACTIVE_DATA) | in ath10k_pci_enable_eeprom()
2985 SM(1, SI_CONFIG_INACTIVE_CLK) | in ath10k_pci_enable_eeprom()
[all …]
/linux/Documentation/devicetree/bindings/display/
H A Dsm501fb.txt1 * SM SM501
3 The SM SM501 is a LCD controller, with proper hardware, it can also
/linux/arch/m68k/fpsp040/
H A Ddecbin.S31 | adds and muls in FP0. Set the sign according to SM.
40 | added if SM = 1 and subtracted if SM = 0. Scale the
43 | SM = 0 a non-zero digit in the integer position
44 | SM = 1 a non-zero digit in Mant0, lsd of the fraction
435 bfextu %d4{#0:#2},%d0 | {FPCR[6],FPCR[5],SM,SE}
/linux/drivers/iio/chemical/
H A DKconfig20 tristate "Atlas Scientific OEM SM sensors"
28 Atlas Scientific OEM SM sensors:
29 * pH SM sensor
30 * EC SM sensor
31 * ORP SM sensor
/linux/arch/arm64/boot/dts/exynos/
H A Dexynos2200-g0s.dts3 * Samsung Galaxy S22+ (g0s/SM-S906B) device tree source
15 model = "Samsung Galaxy S22+ (SM-S906B)";
/linux/arch/arm64/boot/dts/qcom/
H A Dmsm8916-samsung-j3ltetw.dts8 model = "Samsung Galaxy J3 (2016) (SM-J320YZ)";
/linux/arch/arm/boot/dts/samsung/
H A Dexynos4212-tab3-wifi8.dts14 model = "Samsung Galaxy Tab 3 8.0 WiFi (SM-T310) based on Exynos4212";
H A Dexynos4212-tab3-3g8.dts14 model = "Samsung Galaxy Tab 3 8.0 3G (SM-T311) based on Exynos4212";
H A Dexynos4212-tab3-lte8.dts14 model = "Samsung Galaxy Tab 3 8.0 LTE (SM-T315) based on Exynos4212";
/linux/Documentation/admin-guide/nfs/
H A Dnfs-rdma.rst172 If you are using InfiniBand, make sure there is a Subnet Manager (SM)
173 running on the network. If your IB switch has an embedded SM, you can
174 use it. Otherwise, you will need to run an SM, such as OpenSM, on one
177 If an SM is running on your network, you should see the following:
/linux/Documentation/arch/arm64/
H A Dsme.rst21 * PSTATE.SM, PSTATE.ZA, the streaming mode vector length, the ZA and (when
90 * On syscall PSTATE.SM will be cleared and the SVE registers will be handled
97 PSTATE.SM cleared.
108 * Signal handlers are invoked with PSTATE.SM=0, PSTATE.ZA=0, and TPIDR2_EL0=0.
446 * PSTATE.SM, if this is 1 then the PE is in streaming mode. When the value
447 of PSTATE.SM is changed then it is implementation defined if the subset

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