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Searched refs:SDMA0_PHASE1_QUANTUM__VALUE_MASK (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_1_sh_mask.h606 #define SDMA0_PHASE1_QUANTUM__VALUE_MASK … macro
H A Dsdma0_4_0_sh_mask.h607 #define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L macro
H A Dsdma0_4_2_sh_mask.h609 #define SDMA0_PHASE1_QUANTUM__VALUE_MASK … macro
H A Dsdma0_4_2_2_sh_mask.h615 #define SDMA0_PHASE1_QUANTUM__VALUE_MASK … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/oss/
H A Doss_2_0_sh_mask.h1019 #define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0xffff00 macro
H A Doss_2_4_sh_mask.h1109 #define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0xffff00 macro
H A Doss_3_0_1_sh_mask.h1129 #define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0xffff00 macro
H A Doss_3_0_sh_mask.h1635 #define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0xffff00 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/sdma/
H A Dsdma_4_4_0_sh_mask.h302 #define SDMA0_PHASE1_QUANTUM__VALUE_MASK … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_10_1_0_sh_mask.h321 #define SDMA0_PHASE1_QUANTUM__VALUE_MASK … macro
H A Dgc_10_3_0_sh_mask.h322 #define SDMA0_PHASE1_QUANTUM__VALUE_MASK … macro