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Searched refs:RLC_CNTL__RLC_ENABLE_F32_MASK (Results 1 – 17 of 17) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v6_0.c2518 if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) { in gfx_v6_0_halt_rlc()
2519 data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK; in gfx_v6_0_halt_rlc()
2538 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); in gfx_v6_0_rlc_start()
H A Dgfx_v12_1.c1131 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); in gfx_v12_1_rlc_backdoor_autoload_enable()
H A Dgfx_v12_0.c1356 WREG32_SOC15(GC, 0, regRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); in gfx_v12_0_rlc_backdoor_autoload_enable()
H A Dgfx_v9_0.c4893 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK)) in gfx_v9_0_is_rlc_enabled()
/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h7094 #define RLC_CNTL__RLC_ENABLE_F32_MASK 0x00000001L macro
H A Dgfx_7_2_sh_mask.h7667 #define RLC_CNTL__RLC_ENABLE_F32_MASK 0x1 macro
H A Dgfx_8_1_sh_mask.h9031 #define RLC_CNTL__RLC_ENABLE_F32_MASK 0x1 macro
H A Dgfx_8_0_sh_mask.h8477 #define RLC_CNTL__RLC_ENABLE_F32_MASK 0x1 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h22733 #define RLC_CNTL__RLC_ENABLE_F32_MASK … macro
H A Dgc_9_1_sh_mask.h24020 #define RLC_CNTL__RLC_ENABLE_F32_MASK … macro
H A Dgc_9_2_1_sh_mask.h24023 #define RLC_CNTL__RLC_ENABLE_F32_MASK … macro
H A Dgc_9_4_2_sh_mask.h21497 #define RLC_CNTL__RLC_ENABLE_F32_MASK … macro
H A Dgc_11_5_0_sh_mask.h29654 #define RLC_CNTL__RLC_ENABLE_F32_MASK … macro
H A Dgc_11_0_0_sh_mask.h34026 #define RLC_CNTL__RLC_ENABLE_F32_MASK … macro
H A Dgc_12_0_0_sh_mask.h19748 #define RLC_CNTL__RLC_ENABLE_F32_MASK … macro
H A Dgc_10_1_0_sh_mask.h33196 #define RLC_CNTL__RLC_ENABLE_F32_MASK … macro
H A Dgc_11_0_3_sh_mask.h37265 #define RLC_CNTL__RLC_ENABLE_F32_MASK … macro