Home
last modified time | relevance | path

Searched refs:REG_SET_FIELD (Results 1 – 25 of 59) sorted by relevance

123

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfxhub_v2_0.c61 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, in gfxhub_v2_0_get_invalidate_req()
63 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); in gfxhub_v2_0_get_invalidate_req()
64 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); in gfxhub_v2_0_get_invalidate_req()
65 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); in gfxhub_v2_0_get_invalidate_req()
66 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); in gfxhub_v2_0_get_invalidate_req()
67 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); in gfxhub_v2_0_get_invalidate_req()
68 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); in gfxhub_v2_0_get_invalidate_req()
69 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, in gfxhub_v2_0_get_invalidate_req()
193 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v2_0_init_tlb_regs()
194 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in gfxhub_v2_0_init_tlb_regs()
[all …]
H A Dgfxhub_v1_0.c161 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v1_0_init_tlb_regs()
162 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in gfxhub_v1_0_init_tlb_regs()
163 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in gfxhub_v1_0_init_tlb_regs()
165 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in gfxhub_v1_0_init_tlb_regs()
167 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in gfxhub_v1_0_init_tlb_regs()
169 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1); in gfxhub_v1_0_init_tlb_regs()
180 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); in gfxhub_v1_0_init_cache_regs()
181 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); in gfxhub_v1_0_init_cache_regs()
183 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE, in gfxhub_v1_0_init_cache_regs()
185 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0); in gfxhub_v1_0_init_cache_regs()
[all …]
H A Dmmhub_v2_0.c125 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, in mmhub_v2_0_get_invalidate_req()
127 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); in mmhub_v2_0_get_invalidate_req()
128 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); in mmhub_v2_0_get_invalidate_req()
129 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); in mmhub_v2_0_get_invalidate_req()
130 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); in mmhub_v2_0_get_invalidate_req()
131 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); in mmhub_v2_0_get_invalidate_req()
132 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); in mmhub_v2_0_get_invalidate_req()
133 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, in mmhub_v2_0_get_invalidate_req()
235 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2, in mmhub_v2_0_init_system_aperture_regs()
247 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v2_0_init_tlb_regs()
[all …]
H A Dmmhub_v2_3.c64 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, in mmhub_v2_3_get_invalidate_req()
66 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); in mmhub_v2_3_get_invalidate_req()
67 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); in mmhub_v2_3_get_invalidate_req()
68 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); in mmhub_v2_3_get_invalidate_req()
69 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); in mmhub_v2_3_get_invalidate_req()
70 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); in mmhub_v2_3_get_invalidate_req()
71 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); in mmhub_v2_3_get_invalidate_req()
72 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, in mmhub_v2_3_get_invalidate_req()
171 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2, in mmhub_v2_3_init_system_aperture_regs()
183 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v2_3_init_tlb_regs()
[all …]
H A Dhdp_v7_0.c46 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, in hdp_v7_0_update_clock_gating()
51 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, in hdp_v7_0_update_clock_gating()
53 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, in hdp_v7_0_update_clock_gating()
55 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, in hdp_v7_0_update_clock_gating()
57 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, in hdp_v7_0_update_clock_gating()
59 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, in hdp_v7_0_update_clock_gating()
61 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, in hdp_v7_0_update_clock_gating()
63 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, in hdp_v7_0_update_clock_gating()
65 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, in hdp_v7_0_update_clock_gating()
73 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, in hdp_v7_0_update_clock_gating()
[all …]
H A Dhdp_v6_0.c52 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, in hdp_v6_0_update_clock_gating()
60 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, in hdp_v6_0_update_clock_gating()
62 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, in hdp_v6_0_update_clock_gating()
64 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, in hdp_v6_0_update_clock_gating()
66 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, in hdp_v6_0_update_clock_gating()
68 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, in hdp_v6_0_update_clock_gating()
70 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, in hdp_v6_0_update_clock_gating()
72 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, in hdp_v6_0_update_clock_gating()
74 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, in hdp_v6_0_update_clock_gating()
82 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, in hdp_v6_0_update_clock_gating()
[all …]
H A Dhdp_v5_0.c58 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, in hdp_v5_0_update_mem_power_gating()
60 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, in hdp_v5_0_update_mem_power_gating()
66 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, in hdp_v5_0_update_mem_power_gating()
68 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, in hdp_v5_0_update_mem_power_gating()
70 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, in hdp_v5_0_update_mem_power_gating()
72 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, in hdp_v5_0_update_mem_power_gating()
74 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, in hdp_v5_0_update_mem_power_gating()
76 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, in hdp_v5_0_update_mem_power_gating()
78 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, in hdp_v5_0_update_mem_power_gating()
80 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, in hdp_v5_0_update_mem_power_gating()
[all …]
H A Dhdp_v5_2.c69 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, in hdp_v5_2_update_mem_power_gating()
71 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, in hdp_v5_2_update_mem_power_gating()
76 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, in hdp_v5_2_update_mem_power_gating()
78 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, in hdp_v5_2_update_mem_power_gating()
80 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, in hdp_v5_2_update_mem_power_gating()
82 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, in hdp_v5_2_update_mem_power_gating()
84 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, in hdp_v5_2_update_mem_power_gating()
86 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, in hdp_v5_2_update_mem_power_gating()
88 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, in hdp_v5_2_update_mem_power_gating()
90 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, in hdp_v5_2_update_mem_power_gating()
[all …]
H A Dgfxhub_v12_1.c243 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL2, in gfxhub_v12_1_xcc_init_system_aperture_regs()
245 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL2, in gfxhub_v12_1_xcc_init_system_aperture_regs()
263 tmp = REG_SET_FIELD(tmp, in gfxhub_v12_1_xcc_init_tlb_regs()
266 tmp = REG_SET_FIELD(tmp, in gfxhub_v12_1_xcc_init_tlb_regs()
269 tmp = REG_SET_FIELD(tmp, in gfxhub_v12_1_xcc_init_tlb_regs()
272 tmp = REG_SET_FIELD(tmp, in gfxhub_v12_1_xcc_init_tlb_regs()
275 tmp = REG_SET_FIELD(tmp, in gfxhub_v12_1_xcc_init_tlb_regs()
278 tmp = REG_SET_FIELD(tmp, in gfxhub_v12_1_xcc_init_tlb_regs()
296 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, in gfxhub_v12_1_xcc_init_cache_regs()
299 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, in gfxhub_v12_1_xcc_init_cache_regs()
[all …]
H A Dgfxhub_v2_1.c64 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, in gfxhub_v2_1_get_invalidate_req()
66 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); in gfxhub_v2_1_get_invalidate_req()
67 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); in gfxhub_v2_1_get_invalidate_req()
68 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); in gfxhub_v2_1_get_invalidate_req()
69 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); in gfxhub_v2_1_get_invalidate_req()
70 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); in gfxhub_v2_1_get_invalidate_req()
71 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); in gfxhub_v2_1_get_invalidate_req()
72 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, in gfxhub_v2_1_get_invalidate_req()
197 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gfxhub_v2_1_init_tlb_regs()
198 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in gfxhub_v2_1_init_tlb_regs()
[all …]
H A Dnbio_v7_9.c88 REG_SET_FIELD(doorbell_range, DOORBELL0_CTRL_ENTRY_0, in nbio_v7_9_sdma_doorbell_range()
91 REG_SET_FIELD(doorbell_range, DOORBELL0_CTRL_ENTRY_0, in nbio_v7_9_sdma_doorbell_range()
94 REG_SET_FIELD(doorbell_ctrl, S2A_DOORBELL_ENTRY_1_CTRL, in nbio_v7_9_sdma_doorbell_range()
97 REG_SET_FIELD(doorbell_ctrl, S2A_DOORBELL_ENTRY_1_CTRL, in nbio_v7_9_sdma_doorbell_range()
105 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, in nbio_v7_9_sdma_doorbell_range()
108 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, in nbio_v7_9_sdma_doorbell_range()
111 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, in nbio_v7_9_sdma_doorbell_range()
122 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, in nbio_v7_9_sdma_doorbell_range()
125 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, in nbio_v7_9_sdma_doorbell_range()
128 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, in nbio_v7_9_sdma_doorbell_range()
[all …]
H A Dih_v6_1.c101 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2, in force_update_wptr_for_self_int()
103 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2, in force_update_wptr_for_self_int()
105 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, in force_update_wptr_for_self_int()
137 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0)); in ih_v6_1_toggle_ring_interrupts()
140 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0)); in ih_v6_1_toggle_ring_interrupts()
191 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, in ih_v6_1_rb_cntl()
193 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, in ih_v6_1_rb_cntl()
195 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, in ih_v6_1_rb_cntl()
197 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in ih_v6_1_rb_cntl()
201 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, in ih_v6_1_rb_cntl()
[all …]
H A Dgfxhub_v1_2.c177 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2, in gfxhub_v1_2_xcc_init_system_aperture_regs()
206 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in gfxhub_v1_2_xcc_init_tlb_regs()
208 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in gfxhub_v1_2_xcc_init_tlb_regs()
210 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in gfxhub_v1_2_xcc_init_tlb_regs()
212 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in gfxhub_v1_2_xcc_init_tlb_regs()
214 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in gfxhub_v1_2_xcc_init_tlb_regs()
216 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1); in gfxhub_v1_2_xcc_init_tlb_regs()
231 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); in gfxhub_v1_2_xcc_init_cache_regs()
232 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); in gfxhub_v1_2_xcc_init_cache_regs()
234 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE, in gfxhub_v1_2_xcc_init_cache_regs()
[all …]
H A Dlsdma_v7_0.c56 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, BYTE_COUNT, size); in lsdma_v7_0_copy_mem()
57 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, SRC_LOCATION, 0); in lsdma_v7_0_copy_mem()
58 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, DST_LOCATION, 0); in lsdma_v7_0_copy_mem()
59 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, SRC_ADDR_INC, 0); in lsdma_v7_0_copy_mem()
60 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, DST_ADDR_INC, 0); in lsdma_v7_0_copy_mem()
61 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, OVERLAP_DISABLE, 0); in lsdma_v7_0_copy_mem()
62 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, CONSTANT_FILL, 0); in lsdma_v7_0_copy_mem()
88 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, BYTE_COUNT, size); in lsdma_v7_0_fill_mem()
89 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, SRC_LOCATION, 0); in lsdma_v7_0_fill_mem()
90 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, DST_LOCATION, 0); in lsdma_v7_0_fill_mem()
[all …]
H A Dlsdma_v6_0.c56 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, BYTE_COUNT, size); in lsdma_v6_0_copy_mem()
57 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, SRC_LOCATION, 0); in lsdma_v6_0_copy_mem()
58 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, DST_LOCATION, 0); in lsdma_v6_0_copy_mem()
59 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, SRC_ADDR_INC, 0); in lsdma_v6_0_copy_mem()
60 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, DST_ADDR_INC, 0); in lsdma_v6_0_copy_mem()
61 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, OVERLAP_DISABLE, 0); in lsdma_v6_0_copy_mem()
62 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, CONSTANT_FILL, 0); in lsdma_v6_0_copy_mem()
88 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, BYTE_COUNT, size); in lsdma_v6_0_fill_mem()
89 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, SRC_LOCATION, 0); in lsdma_v6_0_fill_mem()
90 tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, DST_LOCATION, 0); in lsdma_v6_0_fill_mem()
[all …]
H A Dmmhub_v1_0.c132 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2, in mmhub_v1_0_init_system_aperture_regs()
144 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in mmhub_v1_0_init_tlb_regs()
145 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in mmhub_v1_0_init_tlb_regs()
146 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in mmhub_v1_0_init_tlb_regs()
148 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in mmhub_v1_0_init_tlb_regs()
150 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, in mmhub_v1_0_init_tlb_regs()
152 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1); in mmhub_v1_0_init_tlb_regs()
166 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); in mmhub_v1_0_init_cache_regs()
167 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); in mmhub_v1_0_init_cache_regs()
169 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE, in mmhub_v1_0_init_cache_regs()
[all …]
H A Dumsch_mm_v4_0.c73 data = REG_SET_FIELD(data, UMSCH_MES_RESET_CTRL, MES_CORE_SOFT_RESET, 0); in umsch_mm_v4_0_load_microcode()
77 data = REG_SET_FIELD(data, VCN_MES_CNTL, MES_INVALIDATE_ICACHE, 1); in umsch_mm_v4_0_load_microcode()
78 data = REG_SET_FIELD(data, VCN_MES_CNTL, MES_PIPE0_RESET, 1); in umsch_mm_v4_0_load_microcode()
79 data = REG_SET_FIELD(data, VCN_MES_CNTL, MES_PIPE0_ACTIVE, 0); in umsch_mm_v4_0_load_microcode()
80 data = REG_SET_FIELD(data, VCN_MES_CNTL, MES_HALT, 1); in umsch_mm_v4_0_load_microcode()
84 data = REG_SET_FIELD(data, VCN_MES_IC_BASE_CNTL, VMID, 0); in umsch_mm_v4_0_load_microcode()
85 data = REG_SET_FIELD(data, VCN_MES_IC_BASE_CNTL, EXE_DISABLE, 0); in umsch_mm_v4_0_load_microcode()
86 data = REG_SET_FIELD(data, VCN_MES_IC_BASE_CNTL, CACHE_POLICY, 0); in umsch_mm_v4_0_load_microcode()
130 data = REG_SET_FIELD(data, UVD_UMSCH_FORCE, IC_FORCE_GPUVM, 1); in umsch_mm_v4_0_load_microcode()
131 data = REG_SET_FIELD(data, UVD_UMSCH_FORCE, DC_FORCE_GPUVM, 1); in umsch_mm_v4_0_load_microcode()
[all …]
H A Dnbif_v6_3_1.c168 doorbell_range = REG_SET_FIELD(doorbell_range, in nbif_v6_3_1_sdma_doorbell_range()
172 doorbell_range = REG_SET_FIELD(doorbell_range, in nbif_v6_3_1_sdma_doorbell_range()
176 doorbell_range = REG_SET_FIELD(doorbell_range, in nbif_v6_3_1_sdma_doorbell_range()
180 doorbell_range = REG_SET_FIELD(doorbell_range, in nbif_v6_3_1_sdma_doorbell_range()
184 doorbell_range = REG_SET_FIELD(doorbell_range, in nbif_v6_3_1_sdma_doorbell_range()
189 doorbell_range = REG_SET_FIELD(doorbell_range, in nbif_v6_3_1_sdma_doorbell_range()
216 doorbell_range = REG_SET_FIELD(doorbell_range, in nbif_v6_3_1_vcn_doorbell_range()
220 doorbell_range = REG_SET_FIELD(doorbell_range, in nbif_v6_3_1_vcn_doorbell_range()
224 doorbell_range = REG_SET_FIELD(doorbell_range, in nbif_v6_3_1_vcn_doorbell_range()
228 doorbell_range = REG_SET_FIELD(doorbell_range, in nbif_v6_3_1_vcn_doorbell_range()
[all …]
H A Diceland_ih.c65 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 1); in iceland_ih_enable_interrupts()
66 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); in iceland_ih_enable_interrupts()
84 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); in iceland_ih_disable_interrupts()
85 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 0); in iceland_ih_disable_interrupts()
121 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0); in iceland_ih_irq_init()
123 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0); in iceland_ih_irq_init()
130 ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 1); in iceland_ih_irq_init()
131 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); in iceland_ih_irq_init()
132 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in iceland_ih_irq_init()
135 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1); in iceland_ih_irq_init()
[all …]
H A Dcz_ih.c65 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 1); in cz_ih_enable_interrupts()
66 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); in cz_ih_enable_interrupts()
84 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); in cz_ih_disable_interrupts()
85 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 0); in cz_ih_disable_interrupts()
121 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0); in cz_ih_irq_init()
123 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0); in cz_ih_irq_init()
130 ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 1); in cz_ih_irq_init()
131 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); in cz_ih_irq_init()
132 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in cz_ih_irq_init()
135 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1); in cz_ih_irq_init()
[all …]
H A Dvpe_v6_1.c80 f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, HALT, halt ? 1 : 0); in vpe_v6_1_halt()
81 f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, TH1_RESET, halt ? 1 : 0); in vpe_v6_1_halt()
110 vpe_colla_cntl = REG_SET_FIELD(vpe_colla_cntl, VPEC_COLLABORATE_CNTL, in vpe_v6_1_set_collaborate_mode()
115 vpe_colla_cfg = REG_SET_FIELD(vpe_colla_cfg, VPEC_COLLABORATE_CFG, MASTER_ID, 0); in vpe_v6_1_set_collaborate_mode()
116 vpe_colla_cfg = REG_SET_FIELD(vpe_colla_cfg, VPEC_COLLABORATE_CFG, MASTER_EN, enable ? 1 : 0); in vpe_v6_1_set_collaborate_mode()
117 vpe_colla_cfg = REG_SET_FIELD(vpe_colla_cfg, VPEC_COLLABORATE_CFG, SLAVE0_ID, 1); in vpe_v6_1_set_collaborate_mode()
118 vpe_colla_cfg = REG_SET_FIELD(vpe_colla_cfg, VPEC_COLLABORATE_CFG, SLAVE0_EN, enable ? 1 : 0); in vpe_v6_1_set_collaborate_mode()
140 ret = REG_SET_FIELD(ret, VPEC_CNTL, UMSCH_INT_ENABLE, 0); in vpe_v6_1_load_microcode()
163 f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, HALT, 0); in vpe_v6_1_load_microcode()
164 f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, TH1_RESET, 0); in vpe_v6_1_load_microcode()
[all …]
H A Damdgpu_amdkfd_gfx_v12.c175 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in wave_control_execute_v12()
177 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in wave_control_execute_v12()
179 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in wave_control_execute_v12()
195 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); in kgd_gfx_v12_enable_debug_trap()
196 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_EN, 0); in kgd_gfx_v12_enable_debug_trap()
197 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_REPLACE, 0); in kgd_gfx_v12_enable_debug_trap()
209 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); in kgd_gfx_v12_disable_debug_trap()
210 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_EN, 0); in kgd_gfx_v12_disable_debug_trap()
211 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_REPLACE, 0); in kgd_gfx_v12_disable_debug_trap()
255 ret = REG_SET_FIELD(0, SPI_GDBG_PER_VMID_CNTL, EXCP_EN, excp_en); in trap_mask_map_sw_to_hw()
[all …]
H A Damdgpu_amdkfd_gfx_v12_1.c178 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in wave_control_execute_v12_1()
180 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in wave_control_execute_v12_1()
182 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in wave_control_execute_v12_1()
198 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); in kgd_gfx_v12_1_enable_debug_trap()
199 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_EN, 0); in kgd_gfx_v12_1_enable_debug_trap()
200 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_REPLACE, 0); in kgd_gfx_v12_1_enable_debug_trap()
212 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); in kgd_gfx_v12_1_disable_debug_trap()
213 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_EN, 0); in kgd_gfx_v12_1_disable_debug_trap()
214 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_REPLACE, 0); in kgd_gfx_v12_1_disable_debug_trap()
258 ret = REG_SET_FIELD(0, SPI_GDBG_PER_VMID_CNTL, EXCP_EN, excp_en); in trap_mask_map_sw_to_hw()
[all …]
H A Dmes_v11_0.c428 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, in mes_v11_0_reset_gfx_pipe_mmio()
430 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, in mes_v11_0_reset_gfx_pipe_mmio()
432 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, in mes_v11_0_reset_gfx_pipe_mmio()
434 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, in mes_v11_0_reset_gfx_pipe_mmio()
438 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, in mes_v11_0_reset_gfx_pipe_mmio()
440 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, in mes_v11_0_reset_gfx_pipe_mmio()
442 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, in mes_v11_0_reset_gfx_pipe_mmio()
444 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, in mes_v11_0_reset_gfx_pipe_mmio()
503 reset_val = REG_SET_FIELD(reset_val, CP_MEC_RS64_CNTL, in mes_v11_0_reset_compute_pipe_mmio()
505 clean_val = REG_SET_FIELD(clean_val, CP_MEC_RS64_CNTL, in mes_v11_0_reset_compute_pipe_mmio()
[all …]
H A Dgfx_v11_0.c2016 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, in gfx_v11_0_select_se_sh()
2019 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, in gfx_v11_0_select_se_sh()
2023 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, in gfx_v11_0_select_se_sh()
2026 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); in gfx_v11_0_select_se_sh()
2029 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, in gfx_v11_0_select_se_sh()
2032 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); in gfx_v11_0_select_se_sh()
2134 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); in gfx_v11_0_init_compute_vmid()
2221 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, in gfx_v11_0_constants_init()
2223 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, in gfx_v11_0_constants_init()
2292 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, in gfx_v11_0_enable_gui_idle_interrupt()
[all …]

123