| /linux/drivers/gpu/drm/amd/display/dc/dce/ |
| H A D | dce_ipp.c | 102 REG_SET_3(CUR_COLOR1, 0, in dce_ipp_cursor_set_attributes()
107 REG_SET_3(CUR_COLOR2, 0, in dce_ipp_cursor_set_attributes()
187 REG_SET_3(DC_LUT_CONTROL, 0, in dce_ipp_program_input_lut()
226 REG_SET_3(DEGAMMA_CONTROL, 0, in dce_ipp_set_degamma()
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| H A D | dce_abm.c | 148 REG_SET_3(DC_ABM1_HG_MISC_CTRL, 0, in dce_abm_init()
153 REG_SET_3(DC_ABM1_IPCSC_COEFF_SEL, 0, in dce_abm_init()
171 REG_SET_3(DC_ABM1_HGLS_REG_READ_PROGRESS, 0, in dce_abm_init()
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| H A D | dce_link_encoder.c | 190 REG_SET_3(DP_DPHY_SYM0, 0, in program_pattern_symbols()
198 REG_SET_3(DP_DPHY_SYM1, 0, in program_pattern_symbols()
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| H A D | dce_transform.c | 240 REG_SET_3(SCL_COEF_RAM_SELECT, 0, in program_multi_taps_filter()
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| /linux/drivers/gpu/drm/amd/display/dc/optc/dcn30/ |
| H A D | dcn30_optc.c | 94 REG_SET_3(OTG_VUPDATE_KEEPOUT, 0, in optc3_lock_doublebuffer_enable()
147 REG_SET_3(OTG_BLANK_DATA_COLOR, 0, in optc3_program_blank_color()
152 REG_SET_3(OTG_BLANK_DATA_COLOR_EXT, 0, in optc3_program_blank_color()
254 REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0, in optc3_set_odm_combine()
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| /linux/drivers/gpu/drm/amd/display/dc/optc/dcn20/ |
| H A D | dcn20_optc.c | 167 REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0, in optc2_set_odm_bypass()
208 REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0, in optc2_set_odm_combine()
430 REG_SET_3(OTG_VUPDATE_KEEPOUT, 0, in optc2_lock_doublebuffer_enable()
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| /linux/drivers/gpu/drm/amd/display/dmub/src/ |
| H A D | dmub_reg.h | 70 #define REG_SET_3(reg, init_value, f1, v1, f2, v2, f3, v3) \ macro
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| /linux/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/ |
| H A D | dcn32_mmhubbub.c | 89 REG_SET_3(MMHUBBUB_WARMUP_CONTROL_STATUS, 0, MMHUBBUB_WARMUP_EN, true, in mmhubbub32_warmup_mcif()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn30/ |
| H A D | dcn30_mmhubbub.c | 89 REG_SET_3(MMHUBBUB_WARMUP_CONTROL_STATUS, 0, MMHUBBUB_WARMUP_EN, true, in mmhubbub3_warmup_mcif()
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| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn10/ |
| H A D | dcn10_dpp_dscl.c | 251 REG_SET_3(SCL_COEF_RAM_TAP_SELECT, 0, in dpp1_dscl_set_scaler_filter()
636 REG_SET_3(DSCL_AUTOCAL, 0, in dpp1_dscl_set_scaler_manual_scale()
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| H A D | dcn10_dpp_cm.c | 780 REG_SET_3(FORMAT_CONTROL, 0, in dpp1_full_bypass()
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| /linux/drivers/gpu/drm/amd/display/dc/hubp/dcn401/ |
| H A D | dcn401_hubp.c | 323 REG_SET_3(DCN_SURF0_TTU_CNTL0, 0, in hubp401_program_deadline()
328 REG_SET_3(DCN_SURF1_TTU_CNTL0, 0, in hubp401_program_deadline()
333 REG_SET_3(DCN_CUR0_TTU_CNTL0, 0, in hubp401_program_deadline()
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| /linux/drivers/gpu/drm/amd/display/dc/hubp/dcn10/ |
| H A D | dcn10_hubp.c | 679 REG_SET_3(DCN_SURF0_TTU_CNTL0, 0, in hubp1_program_deadline()
684 REG_SET_3(DCN_SURF1_TTU_CNTL0, 0, in hubp1_program_deadline()
689 REG_SET_3(DCN_CUR0_TTU_CNTL0, 0, in hubp1_program_deadline()
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| /linux/drivers/gpu/drm/amd/display/dc/hubp/dcn20/ |
| H A D | dcn20_hubp.c | 153 REG_SET_3(DCN_SURF0_TTU_CNTL0, 0, in hubp2_program_deadline()
158 REG_SET_3(DCN_SURF1_TTU_CNTL0, 0, in hubp2_program_deadline()
163 REG_SET_3(DCN_CUR0_TTU_CNTL0, 0, in hubp2_program_deadline()
700 REG_SET_3(DMDATA_QOS_CNTL, 0, in hubp2_dmdata_set_attributes()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn20/ |
| H A D | dcn20_dwb_scl.c | 704 REG_SET_3(WBSCL_COEF_RAM_SELECT, 0, in wbscl_set_scaler_filter()
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| /linux/drivers/gpu/drm/amd/display/dc/optc/dcn35/ |
| H A D | dcn35_optc.c | 92 REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0, in optc35_set_odm_combine()
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