Searched refs:REG_SET_2 (Results 1 – 12 of 12) sorted by relevance
| /linux/drivers/gpu/drm/amd/display/dc/hwss/dce/ |
| H A D | dce_hwseq.c | 71 REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val, in dce_pipe_control_lock()
76 REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val, in dce_pipe_control_lock()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn30/ |
| H A D | dcn30_cm_common.c | 51 REG_SET_2(reg->start_cntl_b, 0, in cm_helper_program_gamcor_xfer_func()
54 REG_SET_2(reg->start_cntl_g, 0, in cm_helper_program_gamcor_xfer_func()
57 REG_SET_2(reg->start_cntl_r, 0, in cm_helper_program_gamcor_xfer_func()
75 REG_SET_2(reg->start_end_cntl2_b, 0, in cm_helper_program_gamcor_xfer_func()
78 REG_SET_2(reg->start_end_cntl2_g, 0, in cm_helper_program_gamcor_xfer_func()
81 REG_SET_2(reg->start_end_cntl2_r, 0, in cm_helper_program_gamcor_xfer_func()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn20/ |
| H A D | dcn20_vmid.c | 88 REG_SET_2(CNTL, 0, in dcn20_vmid_setup()
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn21/ |
| H A D | dcn21_dccg.c | 88 REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0, in dccg21_update_dpp_dto()
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| /linux/drivers/gpu/drm/amd/display/dc/dce/ |
| H A D | dce_stream_encoder.c | 464 REG_SET_2(DP_MSA_TIMING_PARAM1, 0, in dce110_stream_encoder_dp_set_stream_attribute()
489 REG_SET_2(DP_MSA_TIMING_PARAM2, 0, in dce110_stream_encoder_dp_set_stream_attribute()
506 REG_SET_2(DP_MSA_TIMING_PARAM4, 0, in dce110_stream_encoder_dp_set_stream_attribute()
726 REG_SET_2(DP_MSE_RATE_CNTL, 0, in dce110_stream_encoder_set_throttled_vcp_size()
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| /linux/drivers/gpu/drm/amd/display/dmub/src/ |
| H A D | dmub_reg.h | 65 #define REG_SET_2(reg, init_value, f1, v1, f2, v2) \ macro
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn20/ |
| H A D | dcn20_dccg.c | 64 REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0, in dccg2_update_dpp_dto()
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| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn201/ |
| H A D | dcn201_dpp.c | 60 REG_SET_2(FORMAT_CONTROL, 0, in dpp201_cnv_setup()
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| /linux/drivers/gpu/drm/amd/display/dc/gpio/ |
| H A D | hw_ddc.c | 101 REG_SET_2(gpio.MASK_reg, regval, in set_config()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn50/ |
| H A D | dcn50_hwseq.c | 563 REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1); in dcn50_init_hw()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn60/ |
| H A D | dcn60_hwseq.c | 567 REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1); in dcn60_init_hw()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn30/ |
| H A D | dcn30_hwseq.c | 683 REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1); in dcn30_init_hw()
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