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Searched refs:REG_CLR (Results 1 – 5 of 5) sorted by relevance

/linux/arch/arm/mach-imx/
H A Danatop.c17 #define REG_CLR 0x8 macro
46 REG_SET : REG_CLR; in imx_anatop_enable_weak2p5()
52 regmap_write(anatop, ANADIG_REG_CORE + (enable ? REG_SET : REG_CLR), in imx_anatop_enable_fet_odrive()
58 regmap_write(anatop, ANADIG_REG_2P5 + (enable ? REG_SET : REG_CLR), in imx_anatop_enable_2p5_pulldown()
64 regmap_write(anatop, ANADIG_ANA_MISC0 + (enable ? REG_SET : REG_CLR), in imx_anatop_disconnect_high_snvs()
/linux/drivers/gpu/drm/mxsfb/
H A Dmxsfb_drv.c173 writel(CTRL1_CUR_FRAME_DONE_IRQ, mxsfb->base + LCDC_CTRL1 + REG_CLR); in mxsfb_irq_handler()
185 writel(CTRL1_CUR_FRAME_DONE_IRQ_EN, mxsfb->base + LCDC_CTRL1 + REG_CLR); in mxsfb_irq_disable()
186 writel(CTRL1_CUR_FRAME_DONE_IRQ, mxsfb->base + LCDC_CTRL1 + REG_CLR); in mxsfb_irq_disable()
H A Dmxsfb_regs.h13 #define REG_CLR 8 macro
H A Dlcdif_regs.h12 #define REG_CLR 8 macro
/linux/drivers/misc/rp1/
H A Drp1_pci.c22 #define REG_CLR 0xc00 macro
52 iowrite32(value, rp1->bar1 + RP1_PCIE_APBS_BASE + REG_CLR + MSIX_CFG(hwirq)); in msix_cfg_clr()