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Searched refs:REG_CLR (Results 1 – 6 of 6) sorted by relevance

/linux/arch/arm/mach-imx/
H A Danatop.c17 #define REG_CLR 0x8 macro
46 REG_SET : REG_CLR; in imx_anatop_enable_weak2p5()
52 regmap_write(anatop, ANADIG_REG_CORE + (enable ? REG_SET : REG_CLR), in imx_anatop_enable_fet_odrive()
58 regmap_write(anatop, ANADIG_REG_2P5 + (enable ? REG_SET : REG_CLR), in imx_anatop_enable_2p5_pulldown()
64 regmap_write(anatop, ANADIG_ANA_MISC0 + (enable ? REG_SET : REG_CLR), in imx_anatop_disconnect_high_snvs()
/linux/drivers/gpu/drm/mxsfb/
H A Dmxsfb_kms.c215 writel(CTRL_DOTCLK_MODE, mxsfb->base + LCDC_CTRL + REG_CLR); in mxsfb_disable_controller()
238 writel(mask, addr + REG_CLR); in clear_poll_bit()
256 writel(CTRL_CLKGATE, mxsfb->base + LCDC_CTRL + REG_CLR); in mxsfb_reset_block()
269 writel(CTRL1_FIFO_CLEAR, mxsfb->base + LCDC_CTRL1 + REG_CLR); in mxsfb_reset_block()
428 writel(CTRL1_CUR_FRAME_DONE_IRQ, mxsfb->base + LCDC_CTRL1 + REG_CLR); in mxsfb_crtc_enable_vblank()
439 writel(CTRL1_CUR_FRAME_DONE_IRQ_EN, mxsfb->base + LCDC_CTRL1 + REG_CLR); in mxsfb_crtc_disable_vblank()
440 writel(CTRL1_CUR_FRAME_DONE_IRQ, mxsfb->base + LCDC_CTRL1 + REG_CLR); in mxsfb_crtc_disable_vblank()
H A Dmxsfb_drv.c177 writel(CTRL1_CUR_FRAME_DONE_IRQ, mxsfb->base + LCDC_CTRL1 + REG_CLR); in mxsfb_irq_handler()
189 writel(CTRL1_CUR_FRAME_DONE_IRQ_EN, mxsfb->base + LCDC_CTRL1 + REG_CLR); in mxsfb_irq_disable()
190 writel(CTRL1_CUR_FRAME_DONE_IRQ, mxsfb->base + LCDC_CTRL1 + REG_CLR); in mxsfb_irq_disable()
H A Dmxsfb_regs.h13 #define REG_CLR 8 macro
H A Dlcdif_regs.h12 #define REG_CLR 8 macro
H A Dlcdif_kms.c397 writel(CTRL_SW_RESET, lcdif->base + LCDC_V8_CTRL + REG_CLR); in lcdif_reset_block()