Searched refs:PLL_REF_DIV (Results 1 – 5 of 5) sorted by relevance
| /linux/drivers/clk/x86/ |
| H A D | clk-cgu-pll.c | 18 #define PLL_REF_DIV(x) ((x) + 0x08) macro
45 mult = lgm_get_clk_val(pll->membase, PLL_REF_DIV(pll->reg), 0, 12); in lgm_pll_recalc_rate()
46 div = lgm_get_clk_val(pll->membase, PLL_REF_DIV(pll->reg), 18, 6); in lgm_pll_recalc_rate()
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| /linux/drivers/video/fbdev/aty/ |
| H A D | mach64_ct.c | 389 pll->ct.pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par); in aty_get_pll_ct()
515 pll->ct.pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par); in aty_init_pll_ct()
628 aty_st_pll_ct(PLL_REF_DIV, pll->ct.pll_ref_div, par); in aty_resume_pll_ct()
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| /linux/drivers/gpu/drm/bridge/ |
| H A D | chipone-icn6211.c | 85 #define PLL_REF_DIV 0x6b macro
271 * P is pre-divider, register PLL_REF_DIV[3:0] is 1:n divider in chipone_configure_pll()
272 * register PLL_REF_DIV[4] is extra 1:2 divider in chipone_configure_pll()
274 * S is post-divider, register PLL_REF_DIV[7:5] is 2^(n+1) divider in chipone_configure_pll()
288 for (p = p_min; p < p_max; p++) { /* PLL_REF_DIV[4,3:0] */ in chipone_configure_pll()
295 for (s = 0; s < 0x7; s++) { /* PLL_REF_DIV[7:5] */ in chipone_configure_pll()
339 chipone_writeb(icn, PLL_REF_DIV, ref_div); in chipone_configure_pll()
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| /linux/drivers/gpu/drm/amd/display/dc/dce/ |
| H A D | dce_clock_source.c | 1771 calc_pll_cs_init_data.max_pll_ref_divider = clk_src->cs_mask->PLL_REF_DIV; in dce112_clk_src_construct()
1790 calc_pll_cs_init_data_hdmi.max_pll_ref_divider = clk_src->cs_mask->PLL_REF_DIV; in dce112_clk_src_construct()
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| /linux/include/video/ |
| H A D | mach64.h | 782 #define PLL_REF_DIV 0x02 macro
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