Searched refs:PHY_TMR_CFG (Results 1 – 2 of 2) sorted by relevance
57 #define PHY_TMR_CFG 0x9C /* Data lanes timing configuration */ macro
351 dw_update_bits(base + PHY_TMR_CFG, 24, MASK(8), phy->hs2lp_time); in dsi_set_phy_timer()352 dw_update_bits(base + PHY_TMR_CFG, 16, MASK(8), phy->lp2hs_time); in dsi_set_phy_timer()