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Searched refs:PA_CL_UCP_1_W__DATA_REGISTER__SHIFT (Results 1 – 12 of 12) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h5626 #define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT 0x0 macro
H A Dgfx_8_1_sh_mask.h6948 #define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT 0x0 macro
H A Dgfx_8_0_sh_mask.h6414 #define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT 0x0 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h15484 #define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT … macro
H A Dgc_9_1_sh_mask.h16789 #define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT … macro
H A Dgc_9_2_1_sh_mask.h16661 #define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT … macro
H A Dgc_9_4_2_sh_mask.h8910 #define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT … macro
H A Dgc_11_5_0_sh_mask.h16547 #define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT … macro
H A Dgc_11_0_0_sh_mask.h20578 #define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT … macro
H A Dgc_12_0_0_sh_mask.h28251 #define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT … macro
H A Dgc_10_1_0_sh_mask.h22982 #define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT … macro
H A Dgc_11_0_3_sh_mask.h22908 #define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT … macro