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Searched refs:PA_CL_CLIP_CNTL__UCP_ENA_4_MASK (Results 1 – 15 of 15) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h5590 #define PA_CL_CLIP_CNTL__UCP_ENA_4_MASK 0x00000010L macro
H A Dgfx_7_2_sh_mask.h5573 #define PA_CL_CLIP_CNTL__UCP_ENA_4_MASK 0x10 macro
H A Dgfx_8_1_sh_mask.h6895 #define PA_CL_CLIP_CNTL__UCP_ENA_4_MASK 0x10 macro
H A Dgfx_8_0_sh_mask.h6361 #define PA_CL_CLIP_CNTL__UCP_ENA_4_MASK 0x10 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h16916 #define PA_CL_CLIP_CNTL__UCP_ENA_4_MASK macro
H A Dgc_9_1_sh_mask.h18221 #define PA_CL_CLIP_CNTL__UCP_ENA_4_MASK macro
H A Dgc_9_2_1_sh_mask.h18097 #define PA_CL_CLIP_CNTL__UCP_ENA_4_MASK macro
H A Dgc_9_4_3_sh_mask.h20223 #define PA_CL_CLIP_CNTL__UCP_ENA_4_MASK macro
H A Dgc_9_4_2_sh_mask.h10344 #define PA_CL_CLIP_CNTL__UCP_ENA_4_MASK macro
H A Dgc_11_5_0_sh_mask.h18090 #define PA_CL_CLIP_CNTL__UCP_ENA_4_MASK macro
H A Dgc_11_0_0_sh_mask.h22116 #define PA_CL_CLIP_CNTL__UCP_ENA_4_MASK macro
H A Dgc_12_0_0_sh_mask.h30213 #define PA_CL_CLIP_CNTL__UCP_ENA_4_MASK macro
H A Dgc_10_1_0_sh_mask.h24408 #define PA_CL_CLIP_CNTL__UCP_ENA_4_MASK macro
H A Dgc_11_0_3_sh_mask.h24446 #define PA_CL_CLIP_CNTL__UCP_ENA_4_MASK macro
H A Dgc_10_3_0_sh_mask.h22597 #define PA_CL_CLIP_CNTL__UCP_ENA_4_MASK macro