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Searched refs:MMSCH_V4_0_INSERT_DIRECT_WT (Results 1 – 5 of 5) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v4_0_3.c1065 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, in vcn_v4_0_3_start_sriov()
1069 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, in vcn_v4_0_3_start_sriov()
1074 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, in vcn_v4_0_3_start_sriov()
1077 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, in vcn_v4_0_3_start_sriov()
1080 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, in vcn_v4_0_3_start_sriov()
1084 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, in vcn_v4_0_3_start_sriov()
1089 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, in vcn_v4_0_3_start_sriov()
1094 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, in vcn_v4_0_3_start_sriov()
1096 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, in vcn_v4_0_3_start_sriov()
1098 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, in vcn_v4_0_3_start_sriov()
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H A Dvcn_v4_0.c1393 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, in vcn_v4_0_start_sriov()
1396 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, in vcn_v4_0_start_sriov()
1400 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, in vcn_v4_0_start_sriov()
1404 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, in vcn_v4_0_start_sriov()
1407 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, in vcn_v4_0_start_sriov()
1411 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, in vcn_v4_0_start_sriov()
1416 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, in vcn_v4_0_start_sriov()
1421 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, in vcn_v4_0_start_sriov()
1424 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, in vcn_v4_0_start_sriov()
1427 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, in vcn_v4_0_start_sriov()
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H A Dmmsch_v4_0.h115 #define MMSCH_V4_0_INSERT_DIRECT_WT(reg, value) { \ macro
H A Djpeg_v4_0.c474 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(JPEG, 0, in jpeg_v4_0_start_sriov()
477 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(JPEG, 0, in jpeg_v4_0_start_sriov()
480 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(JPEG, 0, in jpeg_v4_0_start_sriov()
H A Djpeg_v4_0_3.c292 MMSCH_V4_0_INSERT_DIRECT_WT(tmp, lower_32_bits(ring->gpu_addr)); in jpeg_v4_0_3_start_sriov()
294 MMSCH_V4_0_INSERT_DIRECT_WT(tmp, upper_32_bits(ring->gpu_addr)); in jpeg_v4_0_3_start_sriov()
296 MMSCH_V4_0_INSERT_DIRECT_WT(tmp, ring->ring_size / 4); in jpeg_v4_0_3_start_sriov()