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Searched refs:MI_LOAD_REGISTER_IMM (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/gpu/drm/xe/
H A Dxe_gt.c284 *cs++ = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(count); in emit_wa_job()
315 *cs++ = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(1); in emit_wa_job()
326 *cs++ = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(2) | in emit_wa_job()
353 *cs++ = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(3) | in emit_wa_job()
364 *cs++ = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(1); in emit_wa_job()
H A Dxe_ring_ops.c54 *cmd++ = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(1) | in __emit_aux_table_inv()
299 dw[i++] = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(2) | MI_LRI_LRM_CS_MMIO; in emit_fake_watchdog()
311 dw[i++] = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(1) | MI_LRI_LRM_CS_MMIO; in emit_fake_watchdog()
H A Dxe_lrc.c211 *regs = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(count); in set_offsets()
672 regs[CTX_LRI_INT_REPORT_PTR] = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(num_regs) | in set_memory_based_intr()
1224 *cmd++ = MI_LOAD_REGISTER_IMM | MI_LRI_LRM_CS_MMIO | MI_LRI_NUM_REGS(1); in setup_invalidate_state_cache_wa()
1582 state_cache_perf_fix[0] = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(1); in xe_lrc_ctx_init()
1975 case MI_LOAD_REGISTER_IMM: in dump_mi_command()
2308 case MI_LOAD_REGISTER_IMM: in xe_lrc_lookup_default_reg_value()
H A Dxe_configfs.c738 MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(1)); in parse_wa_bb_lines()
/linux/drivers/gpu/drm/i915/gem/selftests/
H A Di915_gem_client_blt.c165 *cs++ = MI_LOAD_REGISTER_IMM(1); in prepare_blit()
205 *cs++ = MI_LOAD_REGISTER_IMM(1); in prepare_blit()
/linux/drivers/gpu/drm/i915/gt/
H A Dselftest_workarounds.c580 *cs++ = MI_LOAD_REGISTER_IMM(1); in check_dirty_whitelist()
593 *cs++ = MI_LOAD_REGISTER_IMM(1); in check_dirty_whitelist()
904 *cs++ = MI_LOAD_REGISTER_IMM(whitelist_writable_count(engine)); in scrub_whitelisted_registers()
H A Dintel_gpu_commands.h155 #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*(x)-1) macro
H A Dselftest_execlists.c3083 *cs++ = MI_LOAD_REGISTER_IMM(1); in create_gpr_user()
4250 *cs++ = MI_LOAD_REGISTER_IMM(1); in preserved_virtual_engine()
/linux/drivers/gpu/drm/i915/
H A Di915_cmd_parser.c229 CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, W,
486 CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, W,
1292 if (cmd_desc_is(desc, MI_LOAD_REGISTER_IMM(1)) && in check_cmd()
/linux/drivers/gpu/drm/i915/selftests/
H A Di915_perf.c342 *cs++ = MI_LOAD_REGISTER_IMM(32); in live_noa_gpr()
/linux/drivers/gpu/drm/i915/gem/
H A Di915_gem_execbuffer.c2222 *cs++ = MI_LOAD_REGISTER_IMM(4); in i915_reset_gen7_sol_offsets()