| /linux/arch/arm/kernel/ |
| H A D | entry-ftrace.S | 67 str lr, [sp, #-8]! @ store LR as PC and make space for CPSR/OLD_R0,
68 @ OLD_R0 will overwrite previous LR
70 ldr lr, [sp, #8] @ get previous LR
72 str r0, [sp, #8] @ write r0 as OLD_R0 over previous LR
74 str lr, [sp, #-4]! @ store previous LR as LR
76 add lr, sp, #16 @ move in LR the value of SP as it was
83 @ R0 | R1 | ... | IP | SP + 4 | previous LR | LR | PSR | OLD_R0 |
92 ldr lr, [sp, #S_PC] @ get LR
109 ldr lr, [sp], #4 @ restore LR
132 ldr lr, [sp], #4 @ restore LR
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| H A D | unwind.c | 76 LR = 14, enumerator
371 ctrl->vrs[PC] = ctrl->vrs[LR]; in unwind_exec_insn()
396 ctrl->vrs[FP], ctrl->vrs[SP], ctrl->vrs[LR], ctrl->vrs[PC]); in unwind_exec_insn()
439 ctrl.vrs[LR] = frame->lr; in unwind_frame()
507 ctrl.vrs[PC] = ctrl.vrs[LR]; in unwind_frame()
515 frame->lr = ctrl.vrs[LR]; in unwind_frame()
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| H A D | entry-v7m.S | 53 push {r0, lr} @ preserve LR and original SP
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| H A D | entry-header.S | 173 @ Store/load the USER SP and LR registers by switching to the SYS
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| /linux/tools/perf/arch/arm/tests/ |
| H A D | regs_load.S | 18 #define LR 0x70 macro
55 str lr, [r0, #LR]
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| /linux/arch/powerpc/kernel/ |
| H A D | swsusp_asm64.S | 83 SAVE_SPECIAL(LR)
129 RESTORE_SPECIAL(LR)
263 RESTORE_SPECIAL(LR)
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| /linux/arch/arm/lib/ |
| H A D | backtrace.S | 67 bic sv_pc, sv_pc, mask @ mask PC/LR for the mode
77 bic r1, r1, mask @ mask PC/LR for the mode
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| /linux/net/ieee802154/ |
| H A D | Kconfig | 11 Say Y here to compile LR-WPAN support into the kernel or say M to
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| /linux/arch/arm/mm/ |
| H A D | proc-v7m.S | 134 mov r6, lr @ save LR
143 mov lr, r6 @ restore LR
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| /linux/Documentation/networking/device_drivers/ethernet/intel/ |
| H A D | ixgbe.rst | 59 | LR Modules |
61 | Intel | DUAL RATE 1G/10G SFP+ LR (bailed) | FTLX1471D3BCV-IT |
63 | Intel | DUAL RATE 1G/10G SFP+ LR (bailed) | AFCT-701SDZ-IN2 |
65 | Intel | DUAL RATE 1G/10G SFP+ LR (bailed) | AFCT-701SDDZ-IN1 |
78 | Finisar | SFP+ LR bailed, 10g single rate | FTLX1471D3BCL |
84 | Finisar | DUAL RATE 1G/10G SFP+ LR (No Bail) | FTLX1471D3QCV-IT |
86 | Avago | DUAL RATE 1G/10G SFP+ LR (No Bail) | AFCT-701SDZ-IN1 |
139 - LAN on Motherboard (LOMs) may support DA, SR, or LR modules. Other module
152 | Finisar | SFP+ LR bailed, 10g single rate | FTLX1471D3BCL |
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| /linux/arch/powerpc/platforms/52xx/ |
| H A D | lite5200_sleep.S | 71 SAVE_SPRN(LR, 0x1c)
252 LOAD_SPRN(LR, 0x1c)
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| /linux/Documentation/livepatch/ |
| H A D | reliable-stacktrace.rst | 289 Similarly, a function may deliberately clobber the LR, e.g.
296 ADR LR, <callee>
297 BLR LR
301 The ADR places the address of 'callee' into the LR, before the BLR branches to
308 reliably identify when the LR or stack value should be used (e.g. using
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| H A D | livepatch.rst | 431 Each function has to handle TOC and save LR before it could call
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| /linux/tools/testing/selftests/powerpc/switch_endian/ |
| H A D | check.S | 26 addi r9,r15,32 # check LR
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| /linux/Documentation/arch/arm64/ |
| H A D | gcs.rst | 25 address in the LR is verified against that on the top of the GCS.
56 in LR match those in the GCS, the LR will be ignored. This is not supported
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| /linux/arch/arm/boot/dts/ti/omap/ |
| H A D | omap3-evm-common.dtsi | 105 &gpio1 2 GPIO_ACTIVE_HIGH /* gpio2, lcd LR */
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| /linux/arch/powerpc/platforms/8xx/ |
| H A D | Kconfig | 120 (by not placing conditional branches or branches to LR or CTR
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| /linux/Documentation/arch/powerpc/ |
| H A D | syscall64-abi.rst | 45 stack frame LR and CR save fields are not used.
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| H A D | transactional_memory.rst | 63 Checkpointed registers include all GPRs, FPRs, VRs/VSRs, LR, CCR/CR, CTR, FPCSR
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