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Searched refs:JZ4760_CLK_PLL0_HALF (Results 1 – 2 of 2) sorted by relevance

/linux/drivers/clk/ingenic/
H A Djz4760-cgu.c203 [JZ4760_CLK_PLL0_HALF] = {
216 .parents = { JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1, },
223 .parents = { JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1, },
230 .parents = { JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1, },
248 .parents = { JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1, },
259 JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1 },
267 JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1 },
274 JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1 },
283 .parents = { JZ4760_CLK_EXT, JZ4760_CLK_PLL0_HALF, },
289 .parents = { JZ4760_CLK_EXT, JZ4760_CLK_PLL0_HALF, },
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/linux/include/dt-bindings/clock/
H A Dingenic,jz4760-cgu.h12 #define JZ4760_CLK_PLL0_HALF 3 macro