| /linux/drivers/pinctrl/renesas/ |
| H A D | pfc-r8a77970.c | 60 #define GPSR0_7 F_(DU_DG3, IP0_31_28)
170 #define IP0_31_28 FM(DU_DG3) FM(MSIOF3_SS2) F_(0, 0) FM(A7) FM(PWMFSW0) F_(0, 0) F_(0, 0) F_(0… macro
275 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
420 PINMUX_IPSR_GPSR(IP0_31_28, DU_DG3),
421 PINMUX_IPSR_GPSR(IP0_31_28, MSIOF3_SS2),
422 PINMUX_IPSR_GPSR(IP0_31_28, A7),
423 PINMUX_IPSR_GPSR(IP0_31_28, PWMFSW0),
2232 IP0_31_28
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| H A D | pfc-r8a77980.c | 62 #define GPSR0_7 F_(DU_DG3, IP0_31_28)
204 #define IP0_31_28 FM(DU_DG3) FM(CPG_CPCKOUT) FM(GETHER_RMII_REFCLK) FM(A7) FM(PWMFSW0) F_(0, 0)… macro
325 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
493 PINMUX_IPSR_GPSR(IP0_31_28, DU_DG3),
494 PINMUX_IPSR_GPSR(IP0_31_28, CPG_CPCKOUT),
495 PINMUX_IPSR_GPSR(IP0_31_28, GETHER_RMII_REFCLK),
496 PINMUX_IPSR_GPSR(IP0_31_28, A7),
497 PINMUX_IPSR_GPSR(IP0_31_28, PWMFSW0),
2686 IP0_31_28
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| H A D | pfc-r8a77995.c | 88 #define GPSR1_0 F_(DU_DB0, IP0_31_28)
217 #define IP0_31_28 FM(DU_DB0) FM(LCDOUT0) FM(MSIOF3_TXD_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_… macro
367 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
559 PINMUX_IPSR_GPSR(IP0_31_28, DU_DB0),
560 PINMUX_IPSR_GPSR(IP0_31_28, LCDOUT0),
561 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_TXD_B, SEL_MSIOF3_1),
2673 IP0_31_28
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| H A D | pfc-r8a77965.c | 148 #define GPSR2_1 F_(IRQ1, IP0_31_28)
265 #define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANF… macro
456 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
686 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
687 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
688 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
689 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
690 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
691 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
692 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
[all …]
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| H A D | pfc-r8a77951.c | 143 #define GPSR2_1 F_(IRQ1, IP0_31_28)
260 #define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANF… macro
451 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
680 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
681 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
682 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
683 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
684 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
685 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
686 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
[all …]
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| H A D | pfc-r8a7796.c | 148 #define GPSR2_1 F_(IRQ1, IP0_31_28)
265 #define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANF… macro
456 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
685 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
686 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
687 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
688 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
689 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
690 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
691 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
[all …]
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| H A D | pfc-r8a77990.c | 130 #define GPSR2_8 F_(QSPI1_MISO_IO1, IP0_31_28)
221 #define IP0_31_28 FM(QSPI1_MISO_IO1) FM(RIF2_D0_A) FM(HRX4_B) FM(VI4_DATA2_A) F_(0, 0) F_(0, 0)… macro
393 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
580 PINMUX_IPSR_GPSR(IP0_31_28, QSPI1_MISO_IO1),
581 PINMUX_IPSR_MSEL(IP0_31_28, RIF2_D0_A, SEL_DRIF2_0),
582 PINMUX_IPSR_MSEL(IP0_31_28, HRX4_B, SEL_HSCIF4_1),
583 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA2_A, SEL_VIN4_0),
4789 IP0_31_28
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| H A D | pfc-r8a77470.c | 573 PINMUX_IPSR_GPSR(IP0_31_28, SD0_WP),
574 PINMUX_IPSR_GPSR(IP0_31_28, IRQ7),
575 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_TX_A, SEL_CAN0_0),
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