Home
last modified time | relevance | path

Searched refs:INTR_STATUS (Results 1 – 12 of 12) sorted by relevance

/linux/drivers/i3c/master/mipi-i3c-hci/
H A Dpio.c217 pio_reg_read(INTR_STATUS), pio_reg_read(INTR_SIGNAL_ENABLE)); in hci_pio_cleanup()
252 if (!(pio_reg_read(INTR_STATUS) & STAT_RX_THLD)) in hci_pio_do_rx()
318 if (!(pio_reg_read(INTR_STATUS) & STAT_TX_THLD)) in hci_pio_do_tx()
337 if (!(pio_reg_read(INTR_STATUS) & STAT_TX_THLD)) in hci_pio_do_tx()
479 (pio_reg_read(INTR_STATUS) & STAT_RESP_READY)) { in hci_pio_process_resp()
564 (pio_reg_read(INTR_STATUS) & STAT_CMD_QUEUE_READY)) { in hci_pio_process_cmd()
615 pio_reg_read(INTR_STATUS), pio_reg_read(INTR_SIGNAL_ENABLE)); in hci_pio_queue_xfer()
690 pio_reg_read(INTR_STATUS), pio_reg_read(INTR_SIGNAL_ENABLE)); in hci_pio_dequeue_xfer()
704 if (pio_reg_read(INTR_STATUS) & STAT_RESP_READY) { in hci_pio_err()
737 pio_reg_read(INTR_STATUS), pio_reg_read(INTR_SIGNAL_ENABLE)); in hci_pio_err()
[all …]
H A Dcore.c76 #define INTR_STATUS 0x20 macro
595 val = reg_read(INTR_STATUS); in i3c_hci_irq_handler()
599 reg_write(INTR_STATUS, val); in i3c_hci_irq_handler()
H A Ddma.c751 status = rh_reg_read(INTR_STATUS); in hci_dma_irq_handler()
755 rh_reg_write(INTR_STATUS, status); in hci_dma_irq_handler()
/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hwio.h15 #define INTR_STATUS 0x014 macro
H A Ddpu_hw_interrupts.c62 INTR_STATUS
133 INTR_STATUS
/linux/drivers/net/phy/
H A Dbcm-phy-ptp.c67 #define INTR_STATUS 0x085f macro
236 reg = bcm_phy_read_exp(phydev, INTR_STATUS); in bcm_ptp_framesync_ts()
427 reg = bcm_phy_read_exp(phydev, INTR_STATUS); in bcm_ptp_get_tstamp()
649 reg = bcm_phy_read_exp(phydev, INTR_STATUS); in bcm_ptp_extts_work()
/linux/drivers/media/platform/nvidia/tegra-vde/
H A Dh264.c115 err = readl_relaxed_poll_timeout(vde->bsev + INTR_STATUS, value, in tegra_vde_wait_bsev()
122 err = readl_relaxed_poll_timeout(vde->bsev + INTR_STATUS, value, in tegra_vde_wait_bsev()
132 err = readl_relaxed_poll_timeout(vde->bsev + INTR_STATUS, value, in tegra_vde_wait_bsev()
298 tegra_vde_writel(vde, 0x0003FC00, vde->bsev, INTR_STATUS); in tegra_vde_setup_hw_context()
H A Dvde.h30 #define INTR_STATUS 0x18 macro
/linux/drivers/i3c/master/
H A Ddw-i3c-master.c117 #define INTR_STATUS 0x3c macro
549 writel(INTR_ALL, master->regs + INTR_STATUS); in dw_i3c_master_set_intr_regs()
1480 status = readl(master->regs + INTR_STATUS); in dw_i3c_master_irq_handler()
1483 writel(INTR_ALL, master->regs + INTR_STATUS); in dw_i3c_master_irq_handler()
1490 writel(INTR_TRANSFER_ERR_STAT, master->regs + INTR_STATUS); in dw_i3c_master_irq_handler()
1578 writel(INTR_ALL, master->regs + INTR_STATUS); in dw_i3c_common_probe()
/linux/drivers/mtd/nand/raw/
H A Ddenali.h208 #define INTR_STATUS(bank) (0x410 + (bank) * 0x50) macro
H A Dcadence-nand-controller.c67 #define INTR_STATUS 0x0110 macro
723 writel_relaxed(irq_status->status, cdns_ctrl->reg + INTR_STATUS); in cadence_nand_clear_interrupt()
734 irq_status->status = readl_relaxed(cdns_ctrl->reg + INTR_STATUS); in cadence_nand_read_int_status()
1178 writel_relaxed(0xFFFFFFFF, cdns_ctrl->reg + INTR_STATUS); in cadence_nand_hw_init()
H A Ddenali.c111 iowrite32(irq_status, denali->reg + INTR_STATUS(bank)); in denali_clear_irq()
132 irq_status = ioread32(denali->reg + INTR_STATUS(i)); in denali_isr()