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Searched refs:HIWORD_UPDATE (Results 1 – 24 of 24) sorted by relevance

/linux/drivers/clk/rockchip/
H A Dclk-pll.c221 writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3036_PLLCON0_FBDIV_MASK, in rockchip_rk3036_pll_set_params()
223 HIWORD_UPDATE(rate->postdiv1, RK3036_PLLCON0_POSTDIV1_MASK, in rockchip_rk3036_pll_set_params()
227 writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3036_PLLCON1_REFDIV_MASK, in rockchip_rk3036_pll_set_params()
229 HIWORD_UPDATE(rate->postdiv2, RK3036_PLLCON1_POSTDIV2_MASK, in rockchip_rk3036_pll_set_params()
231 HIWORD_UPDATE(rate->dsmpd, RK3036_PLLCON1_DSMPD_MASK, in rockchip_rk3036_pll_set_params()
279 writel(HIWORD_UPDATE(0, RK3036_PLLCON1_PWRDOWN, 0), in rockchip_rk3036_pll_enable()
290 writel(HIWORD_UPDATE(RK3036_PLLCON1_PWRDOWN, in rockchip_rk3036_pll_disable()
454 writel(HIWORD_UPDATE(RK3066_PLLCON3_RESET, RK3066_PLLCON3_RESET, 0), in rockchip_rk3066_pll_set_params()
458 writel(HIWORD_UPDATE(rate->nr - 1, RK3066_PLLCON0_NR_MASK, in rockchip_rk3066_pll_set_params()
460 HIWORD_UPDATE(rate->no - 1, RK3066_PLLCON0_OD_MASK, in rockchip_rk3066_pll_set_params()
[all …]
H A Dclk-cpu.c199 writel(HIWORD_UPDATE(alt_div, reg_data->div_core_mask[i], in rockchip_cpuclk_pre_rate_change()
209 writel(HIWORD_UPDATE(reg_data->mux_core_alt, in rockchip_cpuclk_pre_rate_change()
214 writel(HIWORD_UPDATE(reg_data->mux_core_alt, in rockchip_cpuclk_pre_rate_change()
251 writel(HIWORD_UPDATE(reg_data->mux_core_main, in rockchip_cpuclk_post_rate_change()
256 writel(HIWORD_UPDATE(reg_data->mux_core_main, in rockchip_cpuclk_post_rate_change()
265 writel(HIWORD_UPDATE(0, reg_data->div_core_mask[i], in rockchip_cpuclk_post_rate_change()
H A Dclk-rk3588.c130 .val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_B0_SEL_CLEAN_MASK, \
132 HIWORD_UPDATE(0, RK3588_CLK_CORE_B0_GPLL_DIV_MASK, \
139 .val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_B1_SEL_CLEAN_MASK, \
146 .val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_B0_SEL_CLEAN_MASK, \
148 HIWORD_UPDATE(0, RK3588_CLK_CORE_B0_GPLL_DIV_MASK, \
155 .val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_B1_SEL_CLEAN_MASK, \
162 .val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_L_SEL_CLEAN_MASK, \
164 HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_L_SEL_CLEAN_MASK, \
171 .val = HIWORD_UPDATE(_seldsu, RK3588_CLK_DSU_DF_SRC_MASK, \
173 HIWORD_UPDATE(_divdsu - 1, RK3588_CLK_DSU_DF_DIV_MASK, \
[all …]
H A Dclk-rk3288.c138 .val = HIWORD_UPDATE(_core_m0, RK3288_DIV_ACLK_CORE_M0_MASK, \
140 HIWORD_UPDATE(_core_mp, RK3288_DIV_ACLK_CORE_MP_MASK, \
146 .val = HIWORD_UPDATE(_l2ram, RK3288_DIV_L2RAM_MASK, \
148 HIWORD_UPDATE(_atclk, RK3288_DIV_ATCLK_MASK, \
150 HIWORD_UPDATE(_pclk_dbg_pre, \
H A Dclk-rk3568.c122 .val = HIWORD_UPDATE(_sclk_core, RK3568_MUX_SCLK_CORE_NPLL_MASK, \
124 HIWORD_UPDATE(_sclk_core, RK3568_MUX_SCLK_CORE_MASK, \
126 HIWORD_UPDATE(1, RK3568_DIV_SCLK_CORE_MASK, \
133 .val = HIWORD_UPDATE(_aclk_core, RK3568_DIV_ACLK_CORE_MASK, \
140 .val = HIWORD_UPDATE(_atclk_core, RK3568_DIV_ATCLK_CORE_MASK, \
142 HIWORD_UPDATE(_gic_core, RK3568_DIV_GICCLK_CORE_MASK, \
149 .val = HIWORD_UPDATE(_pclk_core, RK3568_DIV_PCLK_CORE_MASK, \
151 HIWORD_UPDATE(_periph_core, RK3568_DIV_PERIPHCLK_CORE_MASK, \
H A Dclk-inverter.c49 writel(HIWORD_UPDATE(val, INVERTER_MASK, inv_clock->shift), in rockchip_inv_set_phase()
H A Dclk-rk3036.c86 .val = HIWORD_UPDATE(_core_periph_div, RK3036_DIV_PERI_MASK, \
457 writel_relaxed(HIWORD_UPDATE(0x2, 0x3, 10), in rk3036_clk_init()
H A Dclk-mmc-phase.c145 raw_value = HIWORD_UPDATE(raw_value, 0x07ff, mmc_clock->shift); in rockchip_mmc_set_phase()
H A Dclk-rk3368.c188 .val = HIWORD_UPDATE(_aclkm, RK3368_DIV_ACLKM_MASK, \
194 .val = HIWORD_UPDATE(_atclk, RK3368_DIV_ATCLK_MASK, \
196 HIWORD_UPDATE(_pdbg, RK3368_DIV_PCLK_DBG_MASK, \
H A Dclk-rk3128.c83 .val = HIWORD_UPDATE(_pclk_dbg_div, RK3128_DIV_PERI_MASK, \
85 HIWORD_UPDATE(_core_aclk_div, RK3128_DIV_ACLK_MASK, \
H A Dclk-rk3228.c84 .val = HIWORD_UPDATE(_core_peri_div, RK3228_DIV_PERI_MASK, \
86 HIWORD_UPDATE(_core_aclk_div, RK3228_DIV_ACLK_MASK, \
H A Dclk-rk3576.c119 .val = HIWORD_UPDATE(_amcore - 1, RK3576_ACLK_M_BIGCORE_DIV_MASK, \
126 .val = HIWORD_UPDATE(_amcore - 1, RK3576_ACLK_M_LITCORE_DIV_MASK, \
133 .val = HIWORD_UPDATE(_pclkdbg - 1, RK3576_PCLK_DBG_LITCORE_DIV_MASK, \
140 .val = HIWORD_UPDATE(_ccisel, RK3576_ACLK_CCI_MUX_MASK, \
142 HIWORD_UPDATE(_div - 1, RK3576_ACLK_CCI_DIV_MASK, \
H A Dclk-rk3328.c96 .val = HIWORD_UPDATE(_aclk_core, RK3328_DIV_ACLKM_MASK, \
98 HIWORD_UPDATE(_pclk_dbg, RK3328_DIV_PCLK_DBG_MASK, \
H A Dclk-rk3506.c71 .val = HIWORD_UPDATE(_aclk_core_div, RK3506_DIV_ACLK_CORE_MASK, \
78 .val = HIWORD_UPDATE(_pclk_core_div, RK3506_DIV_PCLK_CORE_MASK, \
H A Dclk-rk3399.c325 .val = HIWORD_UPDATE(_aclkm, RK3399_DIV_ACLKM_MASK, \
331 .val = HIWORD_UPDATE(_atclk, RK3399_DIV_ATCLK_MASK, \
333 HIWORD_UPDATE(_pdbg, RK3399_DIV_PCLK_DBG_MASK, \
H A Dclk-rk3308.c77 .val = HIWORD_UPDATE(_aclk_core, RK3308_DIV_ACLKM_MASK, \
79 HIWORD_UPDATE(_pclk_dbg, RK3308_DIV_PCLK_DBG_MASK, \
H A Dclk-px30.c81 .val = HIWORD_UPDATE(_aclk_core, PX30_DIV_ACLKM_MASK, \
83 HIWORD_UPDATE(_pclk_dbg, PX30_DIV_PCLK_DBG_MASK, \
H A Dclk-rv1126.c89 .val = HIWORD_UPDATE(_aclk_core, RV1126_DIV_ACLK_CORE_MASK, \
91 HIWORD_UPDATE(_pclk_dbg, RV1126_DIV_PCLK_DBG_MASK, \
H A Dclk-rk3528.c61 .val = HIWORD_UPDATE(_aclk_m_core, RK3528_DIV_ACLK_M_CORE_MASK, \
68 .val = HIWORD_UPDATE(_pclk_dbg, RK3528_DIV_PCLK_DBG_MASK, \
H A Dclk-rv1126b.c49 .val = HIWORD_UPDATE(_aclk_core - 1, RV1126B_DIV_ACLK_CORE_MASK, \
56 .val = HIWORD_UPDATE(_pclk_dbg - 1, RV1126B_DIV_PCLK_CORE_MASK, \
H A Dclk-rv1108.c75 .val = HIWORD_UPDATE(_core_peri_div, RV1108_DIV_CORE_MASK,\
H A Dclk.h26 #define HIWORD_UPDATE(val, mask, shift) \ macro
/linux/drivers/phy/rockchip/
H A Dphy-rockchip-inno-csidphy.c78 #define HIWORD_UPDATE(val, mask, shift) \ macro
164 HIWORD_UPDATE(value, reg->mask, reg->shift)); in write_grf_reg()
/linux/drivers/mmc/host/
H A Dsdhci-of-arasan.c99 #define HIWORD_UPDATE(val, mask, shift) \ macro
340 HIWORD_UPDATE(val, GENMASK(width, 0), in sdhci_arasan_syscon_write()