Searched refs:HDMI_1_PLL_CFG_4 (Results 1 – 2 of 2) sorted by relevance
| /linux/drivers/phy/mediatek/ |
| H A D | phy-mtk-hdmi-mt8195.c | 133 mtk_phy_update_field(regs + HDMI_1_PLL_CFG_4, RG_HDMITXPLL_POSDIV_DIV3_CTRL, div3_ctrl_value); in mtk_hdmi_pll_set_hw()
134 mtk_phy_update_field(regs + HDMI_1_PLL_CFG_4, RG_HDMITXPLL_POSDIV, posdiv_vallue); in mtk_hdmi_pll_set_hw()
154 mtk_phy_update_field(regs + HDMI_1_PLL_CFG_4, RG_HDMITXPLL_DIV_CTRL, div_ctrl_value); in mtk_hdmi_pll_set_hw()
185 mtk_phy_update_field(regs + HDMI_1_PLL_CFG_4, RG_HDMITXPLL_PREDIV, prediv_value); in mtk_hdmi_pll_set_hw()
193 mtk_phy_update_field(regs + HDMI_1_PLL_CFG_4, RG_HDMITXPLL_FBKDIV_HIGH, fbkdiv_high); in mtk_hdmi_pll_set_hw()
382 mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_4, DA_HDMITXPLL_PWR_ON); in mtk_hdmi_pll_prepare()
384 mtk_phy_clear_bits(regs + HDMI_1_PLL_CFG_4, DA_HDMITXPLL_ISO_EN); in mtk_hdmi_pll_prepare()
403 mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_4, DA_HDMITXPLL_ISO_EN); in mtk_hdmi_pll_unprepare()
405 mtk_phy_clear_bits(regs + HDMI_1_PLL_CFG_4, DA_HDMITXPLL_PWR_ON); in mtk_hdmi_pll_unprepare()
|
| H A D | phy-mtk-hdmi-mt8195.h | 94 #define HDMI_1_PLL_CFG_4 0x54 macro
|