Searched refs:HDMI_1_CFG_3 (Results 1 – 2 of 2) sorted by relevance
100 mtk_phy_set_bits(regs + HDMI_1_CFG_3, RG_HDMITX21_SLDOLPF_EN); in mtk_hdmi_pll_set_hw()379 mtk_phy_set_bits(regs + HDMI_1_CFG_3, RG_HDMITX21_CKLDO_EN); in mtk_hdmi_pll_prepare()380 mtk_phy_set_bits(regs + HDMI_1_CFG_3, RG_HDMITX21_SLDO_EN); in mtk_hdmi_pll_prepare()398 mtk_phy_clear_bits(regs + HDMI_1_CFG_3, RG_HDMITX21_CKLDO_EN); in mtk_hdmi_pll_unprepare()399 mtk_phy_clear_bits(regs + HDMI_1_CFG_3, RG_HDMITX21_SLDO_EN); in mtk_hdmi_pll_unprepare()
45 #define HDMI_1_CFG_3 0x0c macro