Searched refs:HDMI_1_CFG_10 (Results 1 – 2 of 2) sorted by relevance
51 mtk_phy_clear_bits(regs + HDMI_1_CFG_10, RG_HDMITXPLL_REF_CK_SEL); in mtk_hdmi_pll_sel_src()96 mtk_phy_update_field(regs + HDMI_1_CFG_10, RG_HDMITX21_BIAS_PE_BG_VREF_SEL, 0x2); in mtk_hdmi_pll_set_hw()97 mtk_phy_clear_bits(regs + HDMI_1_CFG_10, RG_HDMITX21_VREF_SEL); in mtk_hdmi_pll_set_hw()99 mtk_phy_clear_bits(regs + HDMI_1_CFG_10, RG_HDMITX21_BIAS_PE_VREF_SELB); in mtk_hdmi_pll_set_hw()377 mtk_phy_clear_bits(regs + HDMI_1_CFG_10, RG_HDMITX21_BG_PWD); in mtk_hdmi_pll_prepare()396 mtk_phy_set_bits(regs + HDMI_1_CFG_10, RG_HDMITX21_BG_PWD); in mtk_hdmi_pll_unprepare()
32 #define HDMI_1_CFG_10 0x40 macro