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Searched refs:GIC_CPU_CTRL (Results 1 – 6 of 6) sorted by relevance

/linux/arch/arm/mach-tegra/
H A Dirq.c51 writel_relaxed(0x1E0, tegra_gic_cpu_base + GIC_CPU_CTRL); in tegra_gic_notifier()
/linux/arch/arm64/kvm/vgic/
H A Dvgic-mmio-v2.c284 case GIC_CPU_CTRL: in vgic_mmio_read_vcpuif()
331 case GIC_CPU_CTRL: in vgic_mmio_write_vcpuif()
467 REGISTER_DESC_WITH_LENGTH(GIC_CPU_CTRL,
/linux/tools/testing/selftests/kvm/aarch64/
H A Dvgic_init.c375 #define GIC_CPU_CTRL 0x00 macro
387 KVM_VGIC_V2_ATTR(GIC_CPU_CTRL, 0)); in test_v2_uaccess_cpuif_no_vcpus()
392 KVM_VGIC_V2_ATTR(GIC_CPU_CTRL, 0), &val); in test_v2_uaccess_cpuif_no_vcpus()
397 KVM_VGIC_V2_ATTR(GIC_CPU_CTRL, 0), &val); in test_v2_uaccess_cpuif_no_vcpus()
/linux/include/linux/irqchip/
H A Darm-gic.h10 #define GIC_CPU_CTRL 0x00 macro
/linux/drivers/irqchip/
H A Dirq-gic.c457 bypass = readl(cpu_base + GIC_CPU_CTRL); in gic_cpu_if_up()
460 writel_relaxed(bypass | mode | GICC_ENABLE, cpu_base + GIC_CPU_CTRL); in gic_cpu_if_up()
536 val = readl(cpu_base + GIC_CPU_CTRL); in gic_cpu_if_down()
538 writel_relaxed(val, cpu_base + GIC_CPU_CTRL); in gic_cpu_if_down()
H A Dirq-hip04.c293 writel_relaxed(1, base + GIC_CPU_CTRL); in hip04_irq_cpu_init()