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Searched refs:GICD_ICPENDR (Results 1 – 5 of 5) sorted by relevance

/linux/include/linux/irqchip/
H A Darm-gic-v3.h26 #define GICD_ICPENDR 0x0280 macro
234 #define GICR_ICPENDR0 GICD_ICPENDR
/linux/tools/testing/selftests/kvm/lib/arm64/
H A Dgic_v3.c273 gicv3_write_reg(intid, GICD_ICPENDR, 32, 1, 1); in gicv3_irq_clear_pending()
/linux/Documentation/virt/kvm/devices/
H A Darm-vgic-v3.rst109 GICR_ISPENDR0, GICD_ICPENDR, and GICR_ICPENDR0. These registers behave
181 Accesses to GICD_ICPENDR register region and GICR_ICPENDR0 registers have
/linux/drivers/irqchip/
H A Dirq-gic-v3.c429 case GICD_ICPENDR: in convert_offset_index()
531 reg = val ? GICD_ISPENDR : GICD_ICPENDR; in gic_irq_set_irqchip_state()
/linux/arch/arm64/kvm/vgic/
H A Dvgic-mmio-v3.c649 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICPENDR,