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Searched refs:GET_INST (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dmmhub_v4_2_0.c79 base = RREG32_SOC15(MMHUB, GET_INST(MMHUB, 0), in mmhub_v4_2_0_get_fb_location()
85 RREG32_SOC15(MMHUB, GET_INST(MMHUB, 0), in mmhub_v4_2_0_get_fb_location()
93 return (u64)RREG32_SOC15(MMHUB, GET_INST(MMHUB, 0), in mmhub_v4_2_0_get_mc_fb_offset()
107 WREG32_SOC15_OFFSET(MMHUB, GET_INST(MMHUB, i), in mmhub_v4_2_0_mid_setup_vm_pt_regs()
112 WREG32_SOC15_OFFSET(MMHUB, GET_INST(MMHUB, i), in mmhub_v4_2_0_mid_setup_vm_pt_regs()
146 WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), in mmhub_v4_2_0_mid_init_gart_aperture_regs()
149 WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), in mmhub_v4_2_0_mid_init_gart_aperture_regs()
153 WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), in mmhub_v4_2_0_mid_init_gart_aperture_regs()
156 WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), in mmhub_v4_2_0_mid_init_gart_aperture_regs()
160 WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), in mmhub_v4_2_0_mid_init_gart_aperture_regs()
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H A Damdgpu_amdkfd_gfx_v9.c54 soc15_grbm_select(adev, mec, pipe, queue, vmid, GET_INST(GC, inst)); in kgd_gfx_v9_lock_srbm()
59 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, inst)); in kgd_gfx_v9_unlock_srbm()
94 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmSH_MEM_CONFIG, sh_mem_config); in kgd_gfx_v9_program_sh_mem_settings()
95 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmSH_MEM_BASES, sh_mem_bases); in kgd_gfx_v9_program_sh_mem_settings()
171 WREG32_SOC15(GC, GET_INST(GC, inst), mmCPC_INT_CNTL, in kgd_gfx_v9_init_interrupts()
238 hqd_base = SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_MQD_BASE_ADDR); in kgd_gfx_v9_hqd_load()
241 reg <= SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_HI); reg++) in kgd_gfx_v9_hqd_load()
248 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_DOORBELL_CONTROL, data); in kgd_gfx_v9_hqd_load()
277 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_LO, in kgd_gfx_v9_hqd_load()
279 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_HI, in kgd_gfx_v9_hqd_load()
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H A Damdgpu_amdkfd_gc_9_4_3.c48 SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, engine_id), in get_sdma_rlc_reg_offset()
228 unsigned int phy_inst = GET_INST(GC, xcc_inst); in kgd_gfx_v9_4_3_set_pasid_vmid_mapping()
299 hqd_base = SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_MQD_BASE_ADDR); in kgd_gfx_v9_4_3_hqd_load()
300 hqd_end = SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_HQD_AQL_DISPATCH_ID_HI); in kgd_gfx_v9_4_3_hqd_load()
309 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_DOORBELL_CONTROL, data); in kgd_gfx_v9_4_3_hqd_load()
338 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_LO, in kgd_gfx_v9_4_3_hqd_load()
340 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_HI, in kgd_gfx_v9_4_3_hqd_load()
342 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_POLL_ADDR, in kgd_gfx_v9_4_3_hqd_load()
344 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_POLL_ADDR_HI, in kgd_gfx_v9_4_3_hqd_load()
346 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_PQ_WPTR_POLL_CNTL1, in kgd_gfx_v9_4_3_hqd_load()
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H A Dgmc_v9_0.c860 tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, sem, GET_INST(GC, inst)); in gmc_v9_0_flush_gpu_tlb()
862 tmp = RREG32_SOC15_IP_NO_KIQ(GC, sem, GET_INST(GC, inst)); in gmc_v9_0_flush_gpu_tlb()
873 WREG32_SOC15_IP_NO_KIQ(MMHUB, req, inv_req, GET_INST(GC, inst)); in gmc_v9_0_flush_gpu_tlb()
875 WREG32_SOC15_IP_NO_KIQ(GC, req, inv_req, GET_INST(GC, inst)); in gmc_v9_0_flush_gpu_tlb()
888 tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, ack, GET_INST(GC, inst)); in gmc_v9_0_flush_gpu_tlb()
890 tmp = RREG32_SOC15_IP_NO_KIQ(GC, ack, GET_INST(GC, inst)); in gmc_v9_0_flush_gpu_tlb()
903 WREG32_SOC15_IP_NO_KIQ(MMHUB, sem, 0, GET_INST(GC, inst)); in gmc_v9_0_flush_gpu_tlb()
905 WREG32_SOC15_IP_NO_KIQ(GC, sem, 0, GET_INST(GC, inst)); in gmc_v9_0_flush_gpu_tlb()
H A Dsoc15_common.h28 #define GET_INST(ip, inst) \ macro
H A Damdgpu_jpeg.c499 inst_id = GET_INST(JPEG, i); in amdgpu_jpeg_dump_ip_state()
H A Damdgpu_xcp.c134 i = GET_INST(GC, (ffs(inst_mask) - 1)); in __amdgpu_xcp_set_unique_id()
H A Damdgpu_device.c934 ret = amdgpu_virt_rlcg_reg_rw(adev, reg, 0, rlcg_flag, GET_INST(GC, xcc_id)); in amdgpu_device_xcc_rreg()
1065 amdgpu_virt_rlcg_reg_rw(adev, reg, v, rlcg_flag, GET_INST(GC, xcc_id)); in amdgpu_device_xcc_wreg()
/linux/drivers/gpu/drm/amd/pm/swsmu/smu13/
H A Dsmu_v13_0_12_ppt.c402 xcc_id = GET_INST(GC, 0); in smu_v13_0_12_get_smu_metrics_data()
789 inst = GET_INST(VCN, k); in smu_v13_0_12_get_xcp_metrics()
813 inst = GET_INST(GC, k); in smu_v13_0_12_get_xcp_metrics()
866 xcc_id = GET_INST(GC, i); in smu_v13_0_12_get_gpu_metrics()
874 inst = GET_INST(VCN, i); in smu_v13_0_12_get_gpu_metrics()
897 gpu_metrics->gfxclk_lock_status = metrics->GfxLockXCDMak >> GET_INST(GC, 0); in smu_v13_0_12_get_gpu_metrics()
934 inst = GET_INST(VCN, i); in smu_v13_0_12_get_gpu_metrics()
948 inst = GET_INST(GC, i); in smu_v13_0_12_get_gpu_metrics()
H A Dsmu_v13_0_6_ppt.c1275 xcc_id = GET_INST(GC, 0); in smu_v13_0_6_get_smu_metrics_data()
2614 inst = GET_INST(VCN, k); in smu_v13_0_6_get_xcp_metrics()
2642 inst = GET_INST(GC, k); in smu_v13_0_6_get_xcp_metrics()
2735 xcc_id = GET_INST(GC, i); in smu_v13_0_6_get_gpu_metrics()
2743 inst = GET_INST(VCN, i); in smu_v13_0_6_get_gpu_metrics()
2770 version) >> GET_INST(GC, 0); in smu_v13_0_6_get_gpu_metrics()
2836 inst = GET_INST(JPEG, i); in smu_v13_0_6_get_gpu_metrics()
2844 inst = GET_INST(VCN, i); in smu_v13_0_6_get_gpu_metrics()
2851 inst = GET_INST(GC, i); in smu_v13_0_6_get_gpu_metrics()
/linux/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_device.c711 mapped_xcc = GET_INST(GC, xcc); in kfd_setup_interrupt_bitmap()
720 mapped_xcc = GET_INST(GC, xcc); in kfd_setup_interrupt_bitmap()