| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/ |
| H A D | dml2_wrapper_fpu.c | 73 in_out_display_cfg->hw.DSCEnabled[i] = mode_support_info->DSCEnabled[i]; in map_hw_resources()
142 p->cur_display_config->output.OutputEncoder[0], p->cur_mode_support_info->DSCEnabled[0]) - 1; in optimize_configuration()
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| H A D | display_mode_core_structs.h | 658 …dml_bool_t DSCEnabled[__DML_NUM_PLANES__]; /// <brief Indicate if the DSC is enabled; used in mode… member
794 …dml_bool_t DSCEnabled[__DML_NUM_PLANES__]; /// <brief Indicate if the DSC is actually required; us… member
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| H A D | display_mode_util.c | 629 dml_print("DML: hw_resource: plane=%d, DSCEnabled = %d\n", i, hw->DSCEnabled[i]); in dml_print_dml_display_cfg_hw_resource()
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| H A D | display_mode_core.c | 737 dml_bool_t DSCEnabled,
5980 dml_bool_t DSCEnabled, in CalculatePrefetchBandwithSupport()
5994 if (DSCEnabled == true && OutputBpp != 0) { in CalculatePrefetchBandwithSupport()
6012 dml_print("DML::%s: DSCEnabled = %u\n", __func__, DSCEnabled); in CalculatePrefetchBandwithSupport()
8368 mode_lib->ms.support.DSCEnabled[k] = mode_lib->ms.RequiresDSC[k]; in dml_core_mode_programming()
8701 if ((mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] != k) || !mode_lib->ms.cache_display_cfg.hw.DSCEnabled[k]) { in dml_core_mode_programming()
8723 locals->DSCDelay[k] = DSCDelayRequirement(mode_lib->ms.cache_display_cfg.hw.DSCEnabled[k], in dml_core_mode_programming()
8738 if (j != k && mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == j && mode_lib->ms.cache_display_cfg.hw.DSCEnabled[j]) in dml_core_mode_programming()
5888 DSCDelayRequirement(dml_bool_t DSCEnabled,enum dml_odm_mode ODMMode,dml_uint_t DSCInputBitPerComponent,dml_float_t OutputBpp,dml_uint_t HActive,dml_uint_t HTotal,dml_uint_t NumberOfDSCSlices,enum dml_output_format_class OutputFormat,enum dml_output_encoder_class Output,dml_float_t PixelClock,dml_float_t PixelClockBackEnd) DSCDelayRequirement() argument
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| H A D | display_mode_vba_util_32.h | 320 unsigned int dml32_DSCDelayRequirement(bool DSCEnabled,
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| H A D | display_mode_vba_32.c | 338 if ((mode_lib->vba.BlendingAndTiming[k] != k) || !mode_lib->vba.DSCEnabled[k]) { in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
368 v->DSCDelay[k] = dml32_DSCDelayRequirement(mode_lib->vba.DSCEnabled[k], in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
379 if (j != k && mode_lib->vba.BlendingAndTiming[k] == j && mode_lib->vba.DSCEnabled[j]) in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3763 mode_lib->vba.DSCEnabled[k] = mode_lib->vba.RequiresDSC[mode_lib->vba.VoltageLevel][k];
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| /linux/drivers/gpu/drm/amd/display/dc/dml/ |
| H A D | display_mode_vba.h | 508 bool DSCEnabled[DC__NUM_DPP__MAX]; member
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| H A D | display_mode_vba.c | 647 mode_lib->vba.DSCEnabled[mode_lib->vba.NumberOfActivePlanes] = dout->dsc_enable; in fetch_pipe_params()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/ |
| H A D | dml2_core_dcn4.c | 632 in_out->mode_support_result.cfg_support_info.stream_support_info[stream_index].dsc_enable = l->mode_support_ex_params.out_evaluation_info->DSCEnabled[i]; in core_dcn4_mode_support()
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| H A D | dml2_core_shared_types.h | 294 bool DSCEnabled[DML2_MAX_PLANES]; /// <brief Indicate if the DSC is actually required; used in mode_programming
293 bool DSCEnabled[DML2_MAX_PLANES]; /// <brief Indicate if the DSC is actually required; used in mode_programming global() member
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| H A D | dml2_core_dcn4_calcs.c | 4537 bool DSCEnabled, in DSCDelayRequirement()
4552 if (DSCEnabled == true && OutputBpp != 0) { in DSCDelayRequirement()
4571 DML_LOG_VERBOSE("DML::%s: DSCEnabled= %u\n", __func__, DSCEnabled); in CalculateSurfaceSizeInMall()
9652 mode_lib->ms.support.DSCEnabled[k] = mode_lib->ms.RequiresDSC[k]; in dml2_core_calcs_mode_support_ex()
9660 DML_LOG_VERBOSE("DML::%s: k=%d, DSCEnabled = %u\n", __func__, k, mode_lib->ms.support.DSCEnabled[k]); in dml2_core_calcs_mode_support_ex()
13152 out->informative.mode_support_info.DSCEnabled[k] = mode_lib->ms.support.DSCEnabled[k]; in dml2_core_calcs_get_informative()
4510 DSCDelayRequirement(bool DSCEnabled,enum dml2_odm_mode ODMMode,unsigned int DSCInputBitPerComponent,double OutputBpp,unsigned int HActive,unsigned int HTotal,unsigned int NumberOfDSCSlices,enum dml2_output_format_class OutputFormat,enum dml2_output_encoder_class Output,double PixelClock,double PixelClockBackEnd) DSCDelayRequirement() argument
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