Searched refs:DP_TRAINING_LANE0_SET (Results 1 – 6 of 6) sorted by relevance
| /linux/drivers/gpu/drm/hisilicon/hibmc/dp/ |
| H A D | dp_link.c | 129 ret = drm_dp_dpcd_write(dp->aux, DP_TRAINING_LANE0_SET, train_set, dp->link.cap.lanes); in hibmc_dp_link_training_cr_pre()
239 ret = drm_dp_dpcd_write(dp->aux, DP_TRAINING_LANE0_SET, dp->link.train_set, in hibmc_dp_link_training_cr()
293 ret = drm_dp_dpcd_write(dp->aux, DP_TRAINING_LANE0_SET, in hibmc_dp_link_training_channel_eq()
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| /linux/include/drm/display/ |
| H A D | drm_dp.h | 619 #define DP_TRAINING_LANE0_SET 0x103 macro
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| /linux/drivers/gpu/drm/gma500/ |
| H A D | cdv_intel_dp.c | 1385 DP_TRAINING_LANE0_SET, in cdv_intel_dplink_set_level()
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| /linux/drivers/gpu/drm/xlnx/ |
| H A D | zynqmp_dp.c | 731 ret = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, train_set, in zynqmp_dp_update_vs_emph()
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| /linux/drivers/gpu/drm/bridge/synopsys/ |
| H A D | dw-dp.c | 583 ret = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, buf, lanes); in dw_dp_link_train_update_vs_emph()
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| /linux/drivers/gpu/drm/bridge/ |
| H A D | tc358767.c | 1214 ret = drm_dp_dpcd_write(aux, DP_TRAINING_LANE0_SET, tmp, 2); in tc_main_link_enable()
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