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Searched refs:DPMTABLE_UPDATE_SCLK (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/gpu/drm/radeon/
H A Dci_dpm.h189 #define DPMTABLE_UPDATE_SCLK 0x00000004 macro
/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dvega12_hwmgr.h176 #define DPMTABLE_UPDATE_SCLK 0x00000004 macro
H A Dvega20_hwmgr.h230 #define DPMTABLE_UPDATE_SCLK 0x00000004 macro
H A Dsmu7_hwmgr.c4116 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK; in smu7_find_dpm_states_clocks_in_dpm_table()
4220 (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) { in smu7_freeze_sclk_mclk_dpm()
4277 (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK)) { in smu7_populate_and_upload_sclk_mclk_dpm_levels()
4376 (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) { in smu7_unfreeze_sclk_mclk_dpm()
H A Dvega10_hwmgr.c3506 (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK | DPMTABLE_UPDATE_SOCCLK)) { in vega10_populate_and_upload_sclk_mclk_dpm_levels()
5625 data->need_update_dpm_table = DPMTABLE_UPDATE_SCLK | in vega10_odn_edit_dpm_table()
/linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dvegam_smumgr.c2205 DPMTABLE_UPDATE_SCLK + in vegam_program_mem_timing_parameters()