Searched refs:DPLL_VCO_ENABLE (Results 1 – 6 of 6) sorted by relevance
224 if ((temp & DPLL_VCO_ENABLE) == 0) { in gma_crtc_dpms()229 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in gma_crtc_dpms()233 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in gma_crtc_dpms()312 if ((temp & DPLL_VCO_ENABLE) != 0) { in gma_crtc_dpms()313 REG_WRITE(map->dpll, temp & ~DPLL_VCO_ENABLE); in gma_crtc_dpms()633 if (crtc_state->saveDPLL & DPLL_VCO_ENABLE) { in gma_crtc_restore()635 crtc_state->saveDPLL & ~DPLL_VCO_ENABLE); in gma_crtc_restore()
210 dpll |= DPLL_VCO_ENABLE; in psb_intel_crtc_mode_set()219 if (dpll & DPLL_VCO_ENABLE) { in psb_intel_crtc_mode_set()221 REG_WRITE(map->dpll, dpll & ~DPLL_VCO_ENABLE); in psb_intel_crtc_mode_set()
759 dpll |= DPLL_VCO_ENABLE; in cdv_intel_crtc_mode_set()769 (REG_READ(map->dpll) & ~DPLL_LOCK) | DPLL_VCO_ENABLE); in cdv_intel_crtc_mode_set()
229 #define DPLL_VCO_ENABLE (1 << 31) macro
1458 (intel_de_read(display, DPLL(display, PIPE_B)) & DPLL_VCO_ENABLE) == 0) in assert_chv_phy_status()
8391 DPLL_VCO_ENABLE; in i830_enable_pipe()