Searched refs:DCSR (Results 1 – 2 of 2) sorted by relevance
2 Debug Control and Status Register (DCSR) Binding16 defined DCSR Memory Map. Child nodes will describe the individual25 The DCSR space exists in the memory-mapped bus.44 range of the DCSR space.57 This node represents the region of DCSR space allocated to the EPU91 offset and length of the DCSR space registers of the device107 This node represents the region of DCSR space allocated to the NPC120 offset and length of the DCSR space registers of the device122 The Nexus Port controller occupies two regions in the DCSR space144 This node represents the region of DCSR space allocated to the NXC[all …]
25 #define DCSR 0x0000 macro314 reg = (phy->idx << 2) + DCSR; in enable_chan()326 reg = (phy->idx << 2) + DCSR; in disable_chan()344 u32 reg = (phy->idx << 2) + DCSR; in clear_chan_irq()