Searched refs:DCLK_VOP1_DIV (Results 1 – 3 of 3) sorted by relevance
132 #define DCLK_VOP1_DIV 183 macro
824 assigned-clocks = <&cru DCLK_VOP1_DIV>, <&cru DCLK_VOP1>,827 assigned-clock-parents = <&cru PLL_GPLL>, <&cru DCLK_VOP1_DIV>;
1195 COMPOSITE(DCLK_VOP1_DIV, "dclk_vop1_div", mux_pll_src_vpll_cpll_gpll_p, 0,