| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| H A D | display_mode_vba_util_32.h | 338 bool DCCEnable[],
436 bool DCCEnable,
511 bool DCCEnable,
791 bool DCCEnable,
901 bool DCCEnable[],
952 bool DCCEnable[],
1039 bool DCCEnable[],
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| H A D | display_mode_vba_util_32.c | 1774 bool DCCEnable[], in dml32_CalculateSurfaceSizeInMall() argument
1832 if (DCCEnable[k] == true) { in dml32_CalculateSurfaceSizeInMall()
1876 if (DCCEnable[k] == true) { in dml32_CalculateSurfaceSizeInMall()
2022 myPipe[k].DCCEnable, in dml32_CalculateVMRowAndSwath()
2096 myPipe[k].DCCEnable, in dml32_CalculateVMRowAndSwath()
2225 myPipe[k].DCCEnable, in dml32_CalculateVMRowAndSwath()
2264 bool DCCEnable, in dml32_CalculateVMAndRowBytes() argument
2372 if (DCCEnable != true) { in dml32_CalculateVMAndRowBytes()
2402 dml_print("DML::%s: DCCEnable = %d\n", __func__, DCCEnable); in dml32_CalculateVMAndRowBytes()
2671 bool DCCEnable, in dml32_CalculateRowBandwidth() argument
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| H A D | display_mode_vba_32.c | 390 mode_lib->vba.DCCEnable, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
439 …ersWatermarksAndPerformanceCalculation.SurfaceParameters[k].DCCEnable = mode_lib->vba.DCCEnable[k]; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
574 if (mode_lib->vba.DCCEnable[k]) in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
779 …refetchParametersWatermarksAndPerformanceCalculation.myPipe.DCCEnable = mode_lib->vba.DCCEnable[k]; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1056 mode_lib->vba.DCCEnable[k], in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1298 mode_lib->vba.DCCEnable, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1349 mode_lib->vba.DCCEnable, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1392 mode_lib->vba.DCCEnable[k], in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1556 mode_lib->vba.DCCEnable, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1620 mode_lib->vba.DCCEnable, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| H A D | display_mode_vba_30.c | 58 unsigned int DCCEnable; member
154 bool DCCEnable,
198 bool DCCEnable,
231 bool DCCEnable,
378 bool DCCEnable[],
427 bool DCCEnable[],
470 bool DCCEnable[],
904 } else if (!myPipe->DCCEnable) in CalculatePrefetchSchedule()
925 if ((v->GPUVMEnable == true || myPipe->DCCEnable == true)) { in CalculatePrefetchSchedule()
1067 if ((v->GPUVMEnable || myPipe->DCCEnable)) { in CalculatePrefetchSchedule()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/ |
| H A D | display_mode_core.c | 235 dml_bool_t DCCEnable,
296 dml_bool_t DCCEnable,
329 dml_bool_t DCCEnable,
505 dml_bool_t DCCEnable[],
556 dml_bool_t DCCEnable[],
670 dml_bool_t DCCEnable[],
1048 dml_print("DML::%s: DCCEnable = %u\n", __func__, p->myPipe->DCCEnable); in CalculatePrefetchSchedule()
1161 } else if (p->GPUVMPageTableLevels == 1 && p->myPipe->DCCEnable != true) { in CalculatePrefetchSchedule()
1167 } else if (p->myPipe->DCCEnable == true) { in CalculatePrefetchSchedule()
1206 if ((p->GPUVMEnable == true || p->myPipe->DCCEnable == true)) { in CalculatePrefetchSchedule()
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| H A D | display_mode_core_structs.h | 469 dml_bool_t DCCEnable; member
591 dml_bool_t DCCEnable[__DML_NUM_PLANES__]; member
1568 dml_bool_t *DCCEnable; member
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| H A D | display_mode_util.c | 600 dml_print("DML: surface_cfg: plane=%d, DCCEnable = %d\n", i, surface->DCCEnable[i]); in dml_print_dml_display_cfg_surface()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/ |
| H A D | display_mode_structs.h | 117 bool DCCEnable; member
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| H A D | display_mode_vba.h | 478 bool DCCEnable[DC__NUM_DPP__MAX]; member
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| H A D | display_mode_vba.c | 609 mode_lib->vba.DCCEnable[mode_lib->vba.NumberOfActivePlanes] = in fetch_pipe_params()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/ |
| H A D | dml2_core_dcn4_calcs.c | 1642 if (!p->DCCEnable || !p->mrq_present) { in CalculateVMAndRowBytes()
1686 DML_LOG_VERBOSE("DML::%s: DCCEnable = %u\n", __func__, p->DCCEnable); in CalculateVMAndRowBytes()
1908 bool DCCEnable, in CalculateRowBandwidth() argument
1925 if (!DCCEnable || !mrq_present) { in CalculateRowBandwidth()
2892 scratch->calculate_vm_and_row_bytes_params.DCCEnable = p->myPipe[k].DCCEnable; in CalculateVMRowAndSwath()
2970 scratch->calculate_vm_and_row_bytes_params.DCCEnable = p->myPipe[k].DCCEnable; in CalculateVMRowAndSwath()
3148 p->myPipe[k].DCCEnable, in CalculateVMRowAndSwath()
5164 DML_LOG_VERBOSE("DML::%s: DCCEnable = %u\n", __func__, p->myPipe->DCCEnable); in CalculatePrefetchSchedule()
7456 myPipe->DCCEnable = display_cfg->plane_descriptors[k].surface.dcc.enable; in dml_core_ms_prefetch_check()
8934 s->SurfParameters[k].DCCEnable = display_cfg->plane_descriptors[k].surface.dcc.enable; in dml_core_mode_support()
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