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Searched refs:CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK (Results 1 – 12 of 12) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h3176 #define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x03000000L macro
H A Dgfx_7_2_sh_mask.h2585 #define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x3000000 macro
H A Dgfx_8_1_sh_mask.h3671 #define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x3000000 macro
H A Dgfx_8_0_sh_mask.h3149 #define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x3000000 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h19413 #define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK … macro
H A Dgc_9_1_sh_mask.h20720 #define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK … macro
H A Dgc_9_2_1_sh_mask.h20647 #define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK … macro
H A Dgc_9_4_2_sh_mask.h12874 #define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK … macro
H A Dgc_11_5_0_sh_mask.h22809 #define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK … macro
H A Dgc_11_0_0_sh_mask.h26797 #define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK … macro
H A Dgc_10_1_0_sh_mask.h27322 #define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK … macro
H A Dgc_11_0_3_sh_mask.h29297 #define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK … macro